Detail publikace

SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

STRAKA, M. KAŠTIL, J. KOTÁSEK, Z.

Originální název

SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent  dynamic reconfiguration of  FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.

Klíčová slova

SEU, simulatotion, generator, framework, online testing, fault tolerance

Autoři

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.

Rok RIV

2011

Vydáno

26. 4. 2011

Nakladatel

IEEE Computer Society

Místo

Oulu

ISBN

978-0-7695-4494-6

Kniha

14th EUROMICRO Conference on Digital System Design

Strany od

223

Strany do

230

Strany počet

8

URL

https://www.fit.vut.cz/research/publication/9585/

BibTex

@inproceedings{BUT76320,
  author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
  title="SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems",
  booktitle="14th EUROMICRO Conference on Digital System Design",
  year="2011",
  pages="223--230",
  publisher="IEEE Computer Society",
  address="Oulu",
  isbn="978-0-7695-4494-6",
  url="https://www.fit.vut.cz/research/publication/9585/"
}