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ZACHARIÁŠOVÁ, M. LENGÁL, O. KAJAN, M.
Originální název
HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware
Typ
článek v časopise - ostatní, Jost
Jazyk
angličtina
Originální abstrakt
Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In this paper we present HAVEN, a freely available open functional verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification runs. HAVEN takes advantage of the inherent parallelism of hardware systems and moves the verified system together with transaction-based interface components of the functional verification environment from software into an FPGA. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM), assertion-based verification, and also provides adequate debugging visibility, making its application range quite large. Our experiments confirm the assumption that the achieved acceleration is proportional to the complexity of the verified system.
Klíčová slova
functional verification, testbench, SystemVerilog, hardware acceleration, FPGA
Autoři
ZACHARIÁŠOVÁ, M.; LENGÁL, O.; KAJAN, M.
Rok RIV
2012
Vydáno
20. 4. 2012
Nakladatel
Springer Verlag
Místo
Berlin
ISSN
0302-9743
Periodikum
Lecture Notes in Computer Science
Ročník
Číslo
7261
Stát
Spolková republika Německo
Strany od
247
Strany do
253
Strany počet
7
BibTex
@article{BUT76422, author="Marcela {Zachariášová} and Ondřej {Lengál} and Michal {Kajan}", title="HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware", journal="Lecture Notes in Computer Science", year="2012", volume="2012", number="7261", pages="247--253", issn="0302-9743" }