Detail publikace

Test Time Reduction by Scan Chain Reordering

BARTOŠ, P.

Originální název

Test Time Reduction by Scan Chain Reordering

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The  principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

Klíčová slova

scan chain, reorganization, reordering, physical layout, fault, diagnostics, test

Autoři

BARTOŠ, P.

Vydáno

28. 4. 2011

Nakladatel

Faculty of Electrical Engineering and Communication BUT

Místo

Brno

ISBN

978-80-214-4273-3

Kniha

Proceedings of the 17th Conference STUDENT EEICT 2011

Edice

Volume 3

Strany od

564

Strany do

568

Strany počet

5

BibTex

@inproceedings{BUT91265,
  author="Pavel {Bartoš}",
  title="Test Time Reduction by Scan Chain Reordering",
  booktitle="Proceedings of the 17th Conference STUDENT EEICT 2011",
  year="2011",
  series="Volume 3",
  pages="564--568",
  publisher="Faculty of Electrical Engineering and Communication BUT",
  address="Brno",
  isbn="978-80-214-4273-3"
}