Detail publikace

Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems

STRNADEL, J.

Originální název

Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, a concept and an early analysis of an embedded hardware/software architecture designed to prevent the software from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the hardware (software) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the actual software load being monitored with no intrusion to the software. According to the actual software load it is able to buffer all interrupts and related data while the software is highly loaded and redirect the interrupts to the MCU as soon as the software becomes underloaded.

Klíčová slova

embedded, limiter, interrupt, overload, monitoring, prevention, real-time

Autoři

STRNADEL, J.

Rok RIV

2012

Vydáno

18. 4. 2012

Nakladatel

IEEE Computer Society

Místo

Tallin

ISBN

978-1-4673-1188-5

Kniha

Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

Strany od

121

Strany do

126

Strany počet

6

URL

https://www.fit.vut.cz/research/publication/9868/

BibTex

@inproceedings{BUT91462,
  author="Josef {Strnadel}",
  title="Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems",
  booktitle="Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)",
  year="2012",
  pages="121--126",
  publisher="IEEE Computer Society",
  address="Tallin",
  doi="10.1109/DDECS.2012.6219037",
  isbn="978-1-4673-1188-5",
  url="https://www.fit.vut.cz/research/publication/9868/"
}

Dokumenty

strnadel_ddecs2012_051.pdf