Detail publikace

Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration

KAŠTIL, J. STRAKA, M. KOTÁSEK, Z.

Originální název

Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.

Klíčová slova

FPGA, partial dynamic reconfiguration, reliability, redundancy, checker, SEU, controller

Autoři

KAŠTIL, J.; STRAKA, M.; KOTÁSEK, Z.

Vydáno

28. 2. 2012

Nakladatel

Politecnico di Milano

Místo

Annecy

Strany od

1

Strany do

4

Strany počet

4

BibTex

@inproceedings{BUT91473,
  author="Jan {Kaštil} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration",
  booktitle="The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)",
  year="2012",
  pages="1--4",
  publisher="Politecnico di Milano",
  address="Annecy"
}