Detail publikace

Generating PWM Signals With Variable Duty From 0% to 100% Based FPGA SPARTAN3AN

NOUMAN, Z. KNOBLOCH, J. KLÍMA, B.

Originální název

Generating PWM Signals With Variable Duty From 0% to 100% Based FPGA SPARTAN3AN

Typ

článek v časopise - ostatní, Jost

Jazyk

angličtina

Originální abstrakt

This article deals with the generation PWM signals with variable duty from 0% to 100% using VHDL and its application in field programmable gate arrays. The article also discusses the usage DCM for decrease the clock frequency. DCM is a digital clock manager that is useful to decrease the skew of clk signal when we want to divide the clk frequency. We used a fixed frequency to produce the input data that generate the PWM signals using one comparator. The comparator compares between two input data. First data is generated using PWM counter and second data is generated by up-down counter using two push buttons. PWM has a fixed frequency and a variable voltage. This voltage value changes for 0V to 2.5 V. Inside signals are monitored on the computer by platform cable usbII and ChipScope program. We need a board fpga and ISE package version14.4.

Klíčová slova

PWM modulator; FPGA

Autoři

NOUMAN, Z.; KNOBLOCH, J.; KLÍMA, B.

Rok RIV

2013

Vydáno

20. 12. 2013

ISSN

1213-1539

Periodikum

Elektrorevue - Internetový časopis (http://www.elektrorevue.cz)

Ročník

4

Číslo

4

Stát

Česká republika

Strany od

1

Strany do

5

Strany počet

5

BibTex

@article{BUT104204,
  author="Ziad {Nouman} and Jan {Knobloch} and Bohumil {Klíma}",
  title="Generating PWM Signals With Variable Duty From 0% to 100% Based FPGA SPARTAN3AN",
  journal="Elektrorevue - Internetový časopis (http://www.elektrorevue.cz)",
  year="2013",
  volume="4",
  number="4",
  pages="1--5",
  issn="1213-1539"
}