Detail publikace

Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier

DEMARTINOS, A. PSYCHALINOS, C. KHATEB, F.

Originální název

Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier

Typ

článek v časopise ve Scopus, Jsc

Jazyk

angličtina

Originální abstrakt

A novel configuration of a four-quadrant current multiplier is introduced in this paper. The realization is achieved through the utilization of the voltage translinear principle; the derived topology simultaneously offers the attractive benefits of ultra-low voltage operation and reduced dc power dissipation, in comparison with the corresponding already published multipliers. The above have been achieved without increasing the circuit complexity. The behavior of the multiplier has been evaluated through simulation results, using the Analog Design Environment and the design kit provided by the TSMC 180nm CMOS process.

Klíčová slova

Analog circuits; CMOS analog integrated circuits; Ultra low-voltage analog circuits; Multipliers.

Autoři

DEMARTINOS, A.; PSYCHALINOS, C.; KHATEB, F.

Rok RIV

2014

Vydáno

11. 2. 2014

Nakladatel

Taylor & Francis

Místo

England

ISSN

2168-1724

Periodikum

International Journal of Electronics Letters

Ročník

2014 (2)

Číslo

4

Stát

Spojené království Velké Británie a Severního Irska

Strany od

224

Strany do

233

Strany počet

10

URL

http://dx.doi.org/10.1080/21681724.2014.900824

BibTex

@article{BUT105548,
  author="Andreas-Christos {Demartinos} and Costas {Psychalinos} and Fabian {Khateb}",
  title="Ultra-Low Voltage CMOS Current-Mode Four-Quadrant Multiplier",
  journal="International Journal of Electronics Letters",
  year="2014",
  volume="2014 (2)",
  number="4",
  pages="224--233",
  doi="10.1080/21681724.2014.900824",
  issn="2168-1724",
  url="http://dx.doi.org/10.1080/21681724.2014.900824"
}