Detail publikace

Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers

MRÁZEK, V. VAŠÍČEK, Z.

Originální název

Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

In order to satisfy a constant need of reducingenergy consumption of electronic devices, the approximate computingparadigm has been introduced in recent years. Thisparadigm is based on the fact that there are applications thatare inherently capable of absorbing some errors in computation.Multimedia signal processing represents a typical example thatallows for quality to be traded off for power.Typically, the approximate circuits are designed at gate level.This paper introduces an automatic design method that is ableto operate directly at transistor level which offers a greatpotential for discovering novel implementations of approximatecircuits. The method combines a stochastic search algorithm withtransistor-level circuit simulator and is able to handle the circuitsconsisting of hundreds of transistors. The goal of the searchstrategy is to improve the power consumption. To estimate powerconsumption, an algorithm based on transistor switching activityis proposed.A design of 4-bit multiplier was chosen as a case study.Two scenarios were considered. Firstly, the proposed methodis applied to improve the power consumption of a common4-bit multiplier and a 4-bit multiplier consisting of manuallydesigned 2-bit multipliers. In both cases, approx. 3% powerreduction was achieved. Then, it is demonstrated that a noticeableimprovement can be obtained when the multipliers are designedusing a hybrid approach operating at transistor as well as gatelevel. We discovered a novel implementation of an approximate4-bit multiplier which has approximately by 40% better powerdelayproduct and exhibits 14% lower worst-case error comparedto the best known 4-bit multiplier consisting of 2-bit manuallyoptimized approximate multipliers

Klíčová slova

Evolutionary optimization, transistor level, low power, approximate computing, multiplier

Autoři

MRÁZEK, V.; VAŠÍČEK, Z.

Rok RIV

2015

Vydáno

8. 3. 2015

Nakladatel

Institute of Electrical and Electronics Engineers

Místo

Porto

ISBN

978-1-4673-8299-1

Kniha

Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing

Strany od

106

Strany do

113

Strany počet

6

URL

http://dx.doi.org/10.1109/EUC.2015.20

BibTex

@inproceedings{BUT119830,
  author="Vojtěch {Mrázek} and Zdeněk {Vašíček}",
  title="Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers",
  booktitle="Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing",
  year="2015",
  pages="106--113",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Porto",
  doi="10.1109/EUC.2015.20",
  isbn="978-1-4673-8299-1",
  url="http://dx.doi.org/10.1109/EUC.2015.20"
}

Dokumenty

euc8299a106.pdf