Detail publikace

Simple two operational transconductance amplifiers-based electronically controllable bilinear two port for fractional-order synthesis

ŠOTNER, R. POLÁK, L. JEŘÁBEK, J. PETRŽELA, J.

Originální název

Simple two operational transconductance amplifiers-based electronically controllable bilinear two port for fractional-order synthesis

Typ

článek v časopise ve Web of Science, Jimp

Jazyk

angličtina

Originální abstrakt

This Letter introduces a new circuit topology of the simple electronically controllable voltage-mode bilinear two port (BTP) employing two operational transconductance amplifiers. The proposed two-port circuit is completely resistorless and contains only a grounded capacitor. It has a high-impedance input (a simple cascading of sections is possible) and allows an independent electronic adjusting of zero and pole frequency of the transfer function. The operation of the BTP circuit is demonstrated for two different locations of the pole and zero frequency coordinates. Moreover, a direct application of four BTPs in fractional-order integrators (order −0.11 and −0.33) with phase shifts −10° and −30° is shown. Design specification is verified by experimental measurements.

Klíčová slova

Bilinear two port, electronic adjusting, fractional-order synthesis, integrator, operational transconductance amplifiers,

Autoři

ŠOTNER, R.; POLÁK, L.; JEŘÁBEK, J.; PETRŽELA, J.

Vydáno

8. 8. 2018

Nakladatel

IET

Místo

The Institution of Engineering and Technology, Michael Faraday House, Six Hills Way, Stevenage, Herts., SG1 2AY, UK

ISSN

0013-5194

Periodikum

Electronics Letters

Ročník

54

Číslo

20

Stát

Spojené království Velké Británie a Severního Irska

Strany od

1164

Strany do

1166

Strany počet

2

URL

https://ieeexplore.ieee.org/document/8475068

BibTex

@article{BUT149311,
  author="Roman {Šotner} and Ladislav {Polák} and Jan {Jeřábek} and Jiří {Petržela}",
  title="Simple two operational transconductance amplifiers-based electronically controllable bilinear two port for fractional-order synthesis",
  journal="Electronics Letters",
  year="2018",
  volume="54",
  number="20",
  pages="1164--1166",
  doi="10.1049/el.2018.5575",
  issn="0013-5194",
  url="https://ieeexplore.ieee.org/document/8475068"
}