Přístupnostní navigace
E-přihláška
Vyhledávání Vyhledat Zavřít
Detail publikace
L. Fujcik, A. S. Kuncheva, T. Mougel, R. Vrba
Originální název
New VHDL Design of Decimation Filter for Sigma-Delta Modulator
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta modulator. Parameters of decimation filter are derived from the specifications of the overall modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 microm technology.
Klíčová slova
VHDL, Design, Decimation Filter, Sigma-Delta Modulator
Autoři
Rok RIV
2005
Vydáno
1. 1. 2005
Nakladatel
Malaysia
Místo
Kuala Lumpur, Malaysie
ISBN
0-7803-9371-6
Kniha
International Conference on Sesnsor and New Techniques in Pharmaceutical and Biomedical Research
Strany od
32
Strany do
35
Strany počet
4
BibTex
@inproceedings{BUT15247, author="Lukáš {Fujcik} and Thibault {Mougel} and Radimír {Vrba}", title="New VHDL Design of Decimation Filter for Sigma-Delta Modulator", booktitle="International Conference on Sesnsor and New Techniques in Pharmaceutical and Biomedical Research", year="2005", pages="4", publisher="Malaysia", address="Kuala Lumpur, Malaysie", isbn="0-7803-9371-6" }