Memory Aware Packet Matching Architecture for High-Speed Networks

článek ve sborníku ve WoS nebo Scopus

angličtina

Packet classification is a crucial operation for manydifferent networking tasks ranging from switching or routing tomonitoring and security devices like firewall or IDS. Generally,accelerated architectures implementing packet classification mustbe used to satisfy ever-growing demands of current high-speednetworks. Furthermore, to keep up with the rising networkthroughputs, the accelerated architectures for FPGAs must beable to classify more than one packet in each clock cycle. This canbe mainly achieved by utilization of multiple processing pipelinesin parallel, what brings replication of FPGA logic and moreimportantly scarce on-chip memory resources.Therefore in this paper, we propose a novel parallel hardwarearchitecture for hash-based exact match classification of multiplepackets per clock cycle with reduced memory replication requirements.The basic idea is to leverage the fact that modern FPGAsoffer hundreds of BlockRAM tiles that can be accessed (addressed)independently to maintain high throughput of matchingeven without fully replicated memory architecture. Our resultsshow that the proposed approach can use memory very efficientlyand scales exceptionally well with increased record capacities. Forexample, the designed architecture is able to achieve throughputof more than 2 Tbps (over 3 000 Mpps) with an effective capacityof more than 40 000 IPv4 flow records for the cost of only366 BlockRAM tiles and around 57 000 LUTs.

packet classification, BRAM, exact match

KEKELY, M.; KEKELY, L.; KOŘENEK, J.

3. 9. 2018

IEEE Computer Society

Praha

978-1-5386-7376-8

Proceedings of the 21st Euromicro Conference on Digital Systems Design

1

8

8

https://www.fit.vut.cz/research/publication/11819/

paper-1.pdf