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PETRŽELA, J. ŠOTNER, R.
Originální název
Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers
Typ
článek v časopise ve Web of Science, Jimp
Jazyk
angličtina
Originální abstrakt
This work describes design process toward fully analogue binary memory where two coupled piecewise-linear (PWL) resistors are implemented using novel network topology with voltage gain amplifiers (VGA). These versatile active devices allow slopes of individual segments of ampere-voltage (AV) characteristics associated with PWL two-terminals to be electronically adjustable via external DC voltage. Numerical analysis of designed memory cell covers all mandatory parts: phase portraits, calculation of the largest Lyapunov exponent (LLE), basins of attraction for the typical strange attractors, and high resolution circuit-oriented bifurcation sequences. A transition from the stable states toward chaotic regime through metastability is proved via real measurement. The robustness of the generated chaotic attractors is verified by captured oscilloscope screenshots.
Klíčová slova
Analogue binary memory; bifurcation diagram; electronic tuning; chaos; Lyapunov exponent; piecewise-linear (PWL) resistors; strange attractor
Autoři
PETRŽELA, J.; ŠOTNER, R.
Vydáno
1. 11. 2020
Nakladatel
IEEE
Místo
Piscataway
ISSN
2169-3536
Periodikum
IEEE Access
Ročník
8
Číslo
1
Stát
Spojené státy americké
Strany od
197276
Strany do
197286
Strany počet
11
URL
https://ieeexplore.ieee.org/document/9244145
Plný text v Digitální knihovně
http://hdl.handle.net/11012/195635
BibTex
@article{BUT165781, author="Jiří {Petržela} and Roman {Šotner}", title="Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers", journal="IEEE Access", year="2020", volume="8", number="1", pages="197276--197286", doi="10.1109/ACCESS.2020.3034665", issn="2169-3536", url="https://ieeexplore.ieee.org/document/9244145" }