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Detail publikace
STRNADEL, J., PEČENKA, T., SEKANINA, L.
Originální název
On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
Use of benchmark designs has become an important part of a process of designing complex systems. However, existing register-transfer level benchmark suites are not sufficient for evaluation of new architectures and tools; synthetic benchmark circuits are an alternative. In the paper, it is demonstrated how evolutionary techniques can be used to generate synthetic benchmarks covering a wide scale of testability properties. The generation process is driven by a register-transfer level testability analysis method and generated benchmarks are stored in synthesizable VHDL source-code. Results gained by proposed method together with future research trends are discussed at the end of the paper.
Klíčová slova
Register-transfer level, synthetic benchmark circuit, testability analysis, evolutionary algorithm
Autoři
Rok RIV
2005
Vydáno
8. 9. 2005
Nakladatel
Slovak University of Technology in Bratislava
Místo
Bratislava
Strany od
107
Strany do
110
Strany počet
4
BibTex
@inproceedings{BUT18046, author="Josef {Strnadel} and Tomáš {Pečenka} and Lukáš {Sekanina}", title="On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits", booktitle="Proceedings of 5th Electronic Circuits and Systems Conference", year="2005", pages="107--110", publisher="Slovak University of Technology in Bratislava", address="Bratislava" }