Detail publikace

Hardware Implementation of ASCON

GERLICH, T. KANDI, A. BAKSI, A. MARTINÁSEK, Z. GUILLEY, S. GAN, P. BREIER, J. CHATTOPADHYAY, A. BHASIN, S. SHRIVASTWA, R.

Originální název

Hardware Implementation of ASCON

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In this work, we present various hardware implementation for ASCON. We cover encryption + tag generation as well as decryption + tag verification for ASCON AEAD and also ASCON hash function. On top the usual (unprotected) implementation, we present side channel protection (threshold countermeasure) and triplication/majority based fault protection. The side channel and fault protections work orthogonal to each other (i.e., either one can be turned on/off without affecting the other). We also show ASIC and FPGA benchmarks for our implementations.

Klíčová slova

ASCON; Hardware Implementation; Side Channel Attack; Threshold Implementation; Fault Attack; Countermeasure

Autoři

GERLICH, T.; KANDI, A.; BAKSI, A.; MARTINÁSEK, Z.; GUILLEY, S.; GAN, P.; BREIER, J.; CHATTOPADHYAY, A.; BHASIN, S.; SHRIVASTWA, R.

Vydáno

21. 6. 2023

Nakladatel

NIST

Strany od

1

Strany do

14

Strany počet

14

URL

https://csrc.nist.gov/events/2023/lightweight-cryptography-workshop-2023

BibTex

@inproceedings{BUT184774,
  author="Tomáš {Gerlich} and Aneesh {Kandi} and Anubhab {Baksi} and Zdeněk {Martinásek} and Sylvain {Guilley} and Peizhou {Gan} and Jakub {Breier} and Anupam {Chattopadhyay} and Shivam {Bhasin} and Ritu Ranjan {Shrivastwa}",
  title="Hardware Implementation of ASCON",
  year="2023",
  pages="1--14",
  publisher="NIST",
  url="https://csrc.nist.gov/events/2023/lightweight-cryptography-workshop-2023"
}