Detail publikace

DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION

A. S. KUNCHEVA, L. FUJCIK, T. MOUGEL, B. DONCHEV, M. HRISTOV

Originální název

DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta modulator. Parameters of decimation filter are derived from the specification of the multibit SD modulator with two-step quantization architecture. Using Matlabtool it is possible to find the filter order, the required quantizationlevel for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA Spartan 3 XC3S200-5FT256.

Klíčová slova

decimation filter, programmable logic device

Autoři

A. S. KUNCHEVA, L. FUJCIK, T. MOUGEL, B. DONCHEV, M. HRISTOV

Rok RIV

2006

Vydáno

1. 1. 2006

Místo

Gdynia

ISBN

83-922632-1-9

Kniha

Proceedings of the International Conference, Mixed Design of Integrated Circuits and Systems

Strany od

83

Strany do

86

Strany počet

4

BibTex

@inproceedings{BUT22118,
  author="Lukáš {Fujcik} and Thibault {Mougel}",
  title="DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION",
  booktitle="Proceedings of the International Conference, Mixed Design of Integrated Circuits and Systems",
  year="2006",
  pages="4",
  address="Gdynia",
  isbn="83-922632-1-9"
}