Detail publikace

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

SEKANINA, L.

Originální název

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

TBD

Klíčová slova

digital circuit, polymorphic gate, adder, testing

Autoři

SEKANINA, L.

Rok RIV

2007

Vydáno

19. 4. 2007

Nakladatel

IEEE Computer Society

Místo

Gliwice

ISBN

1424411610

Kniha

2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

Strany od

243

Strany do

246

Strany počet

4

URL

http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf

BibTex

@inproceedings{BUT28586,
  author="Lukáš {Sekanina}",
  title="Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates",
  booktitle="2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2007",
  pages="243--246",
  publisher="IEEE Computer Society",
  address="Gliwice",
  isbn="1424411610",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf"
}