Detail publikace

DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM

ŠTEFFAN, P. ZOŠIAK, D.

Originální název

DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This application note contains detail description and implementation of digital phase-locked loop (for short DPLL) designed by using VHSIC hardware description language (for short VHDL). This programming language was developed for hardware design of microchips and digital circuits, later adapted for programming FPGA and CPLD circuits. FPGAs and CPLDs are very useful for making design models, so we are able to test the design before fabrication. DPLL is analogous to PLL constructed from analog electronic components. Wide usage (FM demodulation, FSK demodulation, tone decoding, frequency multiplication, clock synchronization) makes from DPLL or PLL important electronic component in signal processing and digital systems. Design described in this paper was used as clock recovery and input data synchronization system by implementation of USB protocol into FPGA circuit again by using VHD language.

Klíčová slova

synchronization, recovery, VHDL, CPLL, FPGA

Autoři

ŠTEFFAN, P.; ZOŠIAK, D.

Vydáno

10. 9. 2009

Nakladatel

Ing. Zdeněk Novotný

Místo

Brno

ISBN

978-80-214-3717-3

Kniha

Electronic Devices and Systems EDS 08

Edice

první

Číslo edice

1

Strany od

383

Strany do

389

Strany počet

7

BibTex

@inproceedings{BUT30787,
  author="Pavel {Šteffan} and Dušan {Zošiak}",
  title="DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM",
  booktitle="Electronic Devices and Systems EDS 08",
  year="2009",
  series="první",
  number="1",
  pages="383--389",
  publisher="Ing. Zdeněk Novotný",
  address="Brno",
  isbn="978-80-214-3717-3"
}