Detail publikace

The Design of Hardware Checkers for Verification and Diagnostic Purposes

STRAKA, M. KOTÁSEK, Z. WINTER, J.

Originální název

The Design of Hardware Checkers for Verification and Diagnostic Purposes

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers of digital components is described. First, our experiments with PSL language and FoCs tool are demonstrated. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principles of our approach based on developing a formal language to describe the functions to be checked and a compiler which transforms the description into VHDL code are explained.

Klíčová slova

on-line checker, on-line testing, verification, PSL, FPGA, FoCs, ModelSim

Autoři

STRAKA, M.; KOTÁSEK, Z.; WINTER, J.

Rok RIV

2008

Vydáno

25. 6. 2008

Nakladatel

The University of Technology Košice

Místo

High Tatras - Stará Lesná

ISBN

978-80-8086-092-9

Kniha

CSE'2008 International Scientific Conference on Computer Science and Engineering

Strany od

320

Strany do

327

Strany počet

7

URL

https://www.fit.vut.cz/research/publication/8646/

BibTex

@inproceedings{BUT32103,
  author="Martin {Straka} and Zdeněk {Kotásek} and Jan {Winter}",
  title="The Design of Hardware Checkers for Verification and Diagnostic Purposes",
  booktitle="CSE'2008 International Scientific Conference on Computer Science and Engineering",
  year="2008",
  pages="320--327",
  publisher="The University of Technology Košice",
  address="High Tatras - Stará Lesná",
  isbn="978-80-8086-092-9",
  url="https://www.fit.vut.cz/research/publication/8646/"
}