Detail publikace

Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time

ŠIMÁČEK, J. SEKANINA, L. STAREČEK, L.

Originální název

Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Recently, a method has been presented that allows a significant test application time reduction if some of gates of a digital circuit are reconfigured before test is applied. Selection of the gates for reconfiguration was performed using a very time consuming deterministic recursive search algorithm. In this paper, a new method is proposed for selection of the gates in order to reduce the test application time. The method utilizes an evolutionary algorithm which is able to discover very competitive reconfiguration strategies while the time of optimization is considerably reduced with respect to the original algorithm. Moreover, the user can easily balance the trade off between the number of test vectors and amount of logic that has to be reconfigured. Experimental results are reported for the ISCAS85 benchmark suite.

Klíčová slova

evolutionary algorithm, reconfiguration, testing, digital circuit

Autoři

ŠIMÁČEK, J.; SEKANINA, L.; STAREČEK, L.

Rok RIV

2010

Vydáno

8. 9. 2010

Nakladatel

Springer Verlag

Místo

Berlin

ISBN

978-3-642-15322-8

Kniha

Evolvable Systems: From Biology to Hardware

Edice

Lecture Notes in Computer Science

Strany od

214

Strany do

225

Strany počet

12

URL

BibTex

@inproceedings{BUT34847,
  author="Jiří {Šimáček} and Lukáš {Sekanina} and Lukáš {Stareček}",
  title="Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time",
  booktitle="Evolvable Systems: From Biology to Hardware",
  year="2010",
  series="Lecture Notes in Computer Science",
  volume="6274",
  pages="214--225",
  publisher="Springer Verlag",
  address="Berlin",
  isbn="978-3-642-15322-8",
  url="https://www.fit.vut.cz/research/publication/9300/"
}