Statistical Analysis of Blind-Oversampling CDR Circuits

článek ve sborníku ve WoS nebo Scopus

angličtina

The paper deals with two statistical simulation models for feed-forward blind-oversampling Clock and Data Recovery circuits, which determine the center of the data eye by observing the positions of edges in a data stream. The first model describes the traditional averaged phase picking method based on counting the edges in several domains, which divide the signal period. The second model was developed for a newly proposed CDR circuit, which selects the optimum sampling phase upon the occurrence of several consecutive edges in one sampling domain. Its simulation model is based on the periodic Markov chain representation of the domain-selection process. The averaged Bit-Error Rate can be simply computed from the steady-state of the chain. The computational complexity of statistical models is determined by the added jitter properties rather than by the actual level of bit-error rate. The models include random jitter, sinusoidal jitter, and frequency offset of transmit and receive clocks.

blind oversampling CDR; jitter tolerance; statistical methods;

KOLKA, Z.; KUBÍČEK, M.; BIOLKOVÁ, V.; BIOLEK, D.

2012

3. 10. 2012

IEEE

Saint Petersburg, Russia

978-1-4673-2015-3

Proceedings of Int. Congress on Ultra Modern Telecommunications and Control Systems (ICUMT 2012)

497

501

5