Detail publikace

Implementation Techniques for Evolvable HW Systems: Virtual vs. Dynamic Reconfiguration

SALVADOR, R. OTERO, A. MORA, J. DE LA TORRE, E. RIESGO, T. SEKANINA, L.

Originální název

Implementation Techniques for Evolvable HW Systems: Virtual vs. Dynamic Reconfiguration

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Adaptive hardware requires some reconfiguration capabilities. FPGAs with native dynamic partial reconfiguration (DPR) support pose a dilemma for system designers: whether to use native DPR or to build a virtual reconfigurable circuit (VRC) on top of the FPGA which allows selecting alternative functions by a multiplexing scheme. This solution allows much faster reconfiguration, but with higher resource overhead. This paper discusses the advantages of both implementations for a 2D image processing matrix. Results show how higher operating frequency is obtained for the matrix using DPR. However, this is compensated in the VRC during evolution due to the comparatively negligible reconfiguration time. Regarding area, the DPR implementation consumes slightly more resources due to the reconfiguration engine, but adds further more capabilities to the system.

Klíčová slova

FPGA, evolvable hardware, digital circuit, image filter

Autoři

SALVADOR, R.; OTERO, A.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L.

Rok RIV

2012

Vydáno

29. 8. 2012

Nakladatel

IEEE Computer Society

Místo

Oslo

ISBN

978-1-4673-2257-7

Kniha

Proc. of the 22nd International Conference on Field Programmable Logic and Applications (FPL)

Strany od

547

Strany do

550

Strany počet

4

URL

https://www.fit.vut.cz/research/publication/9985/

BibTex

@inproceedings{BUT96954,
  author="Ruben {Salvador} and Andres {Otero} and Javier {Mora} and Eduardo {De la Torre} and Teresa {Riesgo} and Lukáš {Sekanina}",
  title="Implementation Techniques for Evolvable HW Systems: Virtual vs. Dynamic Reconfiguration",
  booktitle="Proc. of the 22nd International Conference on Field Programmable Logic and Applications (FPL)",
  year="2012",
  pages="547--550",
  publisher="IEEE Computer Society",
  address="Oslo",
  doi="10.1109/FPL.2012.6339376",
  isbn="978-1-4673-2257-7",
  url="https://www.fit.vut.cz/research/publication/9985/"
}