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ZACHARIÁŠOVÁ, M.
Originální název
Acceleration of Functional Verification in the Development Cycle of Hardware Systems
Typ
článek ve sborníku mimo WoS a Scopus
Jazyk
angličtina
Originální abstrakt
Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. I introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.The second approach utilizes genetic algorithm in order to optimize and automate a technique called coverage-driven verification.
Klíčová slova
functional verification, hardware acceleration, genetic algorithm, optimization
Autoři
Rok RIV
2012
Vydáno
12. 9. 2012
Nakladatel
Czech Technical University
Místo
Praha
ISBN
978-80-01-05106-1
Kniha
Počítačové architektury a diagnostika
Strany od
73
Strany do
78
Strany počet
6
BibTex
@inproceedings{BUT97039, author="Marcela {Zachariášová}", title="Acceleration of Functional Verification in the Development Cycle of Hardware Systems", booktitle="Počítačové architektury a diagnostika", year="2012", pages="73--78", publisher="Czech Technical University", address="Praha", isbn="978-80-01-05106-1" }