Detail publikace

Low-Latency Modular Packet Header Parser for FPGA

KEKELY, L. PUŠ, V. KOŘENEK, J.

Originální název

Low-Latency Modular Packet Header Parser for FPGA

Typ

článek ve sborníku mimo WoS a Scopus

Jazyk

angličtina

Originální abstrakt

Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols.

Klíčová slova

Packet Parsing, Latency, FPGA

Autoři

KEKELY, L.; PUŠ, V.; KOŘENEK, J.

Rok RIV

2012

Vydáno

23. 11. 2012

Nakladatel

Association for Computing Machinery

Místo

Austin

ISBN

978-1-4503-1685-9

Kniha

ACM/IEEE Symposium on Architectures for Networking and Communications Systems

Strany od

77

Strany do

78

Strany počet

2

URL

https://www.fit.vut.cz/research/publication/10197/

BibTex

@inproceedings{BUT97063,
  author="Lukáš {Kekely} and Viktor {Puš} and Jan {Kořenek}",
  title="Low-Latency Modular Packet Header Parser for FPGA",
  booktitle="ACM/IEEE Symposium on Architectures for Networking and Communications Systems",
  year="2012",
  pages="77--78",
  publisher="Association for Computing Machinery",
  address="Austin",
  isbn="978-1-4503-1685-9",
  url="https://www.fit.vut.cz/research/publication/10197/"
}