Publications

• 2024

  KLHŮFEK, J.; ŠAFÁŘ, M.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024. p. 1-6. ISBN: 979-8-3503-5934-3.
  Detail | WWW

• 2022

  KLHŮFEK, J.; MRÁZEK, V. ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22). Prague: Institute of Electrical and Electronics Engineers, 2022. p. 44-47. ISBN: 978-1-6654-9431-1.
  Detail | WWW

*) Publications are generated once a 24 hours.