Curriculum vitae

Education and academic qualification

• 2019 - Ph.D., Computer Science and Engineering, FIT BUT, Czech Republic (Ph.D. thesis)
• 2011 - Ing., Mathematical Methods in Information Technology, FIT BUT, Czech Republic (Master's thesis)
• 2009 - Erasmus student exchange, Lappeenranta University of Technology, Finland
• 2009 - Bc., Information Technology, FIT BUT, Czech Republic (Bachelor's thesis)

• 06/2017 - Quartus Prime Workshop, El Camino, Mainburg, Germany
• 12/2013 - Vivado Advanced XDC and STA, Doulos, Ringwood, United Kingdom
• 11/2012 - Essential Tcl Scripting for the Vivado Design Suite, so-logic, Vienna, Austria
• 05/2009 - CCNA Exploration: Accessing the WAN, FIT BUT, Czech Republic
• 12/2008 - CCNA Exploration: LAN Switching and Wireless, FIT BUT, Czech Republic
• 10/2008 - CCNA Exploration: Routing Protocols and Concepts, FIT BUT, Czech Republic
• 10/2008 - CCNA Exploration: Network Fundamentals, FIT BUT, Czech Republic

Career overview

• 01/2019 - present, FW Devel. Group Leader, Security and Administration Tools Department, CESNET, Czech Republic
• 01/2016 - present, Junior Researcher, Research Centre of Information Technology, FIT BUT, Czech Republic
• 01/2015 - 12/2018, Researcher, Security and Administration Tools Department, CESNET, Czech Republic
• 10/2014 - 12/2014, Visiting Researcher, Computer Laboratory, University of Cambridge, United Kingdom
• 01/2014 - 09/2014, Junior Researcher, Research Centre of Information Technology, FIT BUT, Czech Republic
• 07/2012 - 12/2012, Junior Researcher, Research Centre of Information Technology, FIT BUT, Czech Republic
• 09/2011 - present, Assistant Lecturer, FIT BUT, Czech Republic
• 08/2011 - 09/2014, Researcher, Security and Administration Tools Department, CESNET, Czech Republic
• 10/2007 - 12/2010, VHDL Developer, Liberouter project

Scientific activities

• hardware acceleration of network algorithms using FPGA
• generation of synthetic data sets for network algorithms benchmarking