Publications

• 2023

  KOŠAŘ, V.; ŠIŠMIŠ, L.; MATOUŠEK, J.; KOŘENEK, J. Accelerating IDS Using TLS Pre-Filter in FPGA. In Proceedings - IEEE Symposium on Computers and Communications. Tunis: IEEE Computer Society, 2023. p. 436-442. ISBN: 979-8-3503-0048-2.
  Detail | WWW

• 2020

  FUKAČ, T.; KOŠAŘ, V.; KOŘENEK, J.; MATOUŠEK, J. Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-Filter. In Proceedings - Conference on Local Computer Networks, LCN. Sydney (virtual): Institute of Electrical and Electronics Engineers, 2020. p. 509-514. ISBN: 978-1-7281-7158-6.
  Detail

• 2016

  KOŠAŘ, V.; KOŘENEK, J. Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. In Proceedings of The 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016. p. 591-598. ISBN: 978-1-5090-2816-0.
  Detail

  GROCHOL, D.; SEKANINA, L.; KOŘENEK, J.; ŽÁDNÍK, M.; KOŠAŘ, V. Evolutionary Circuit Design for Fast FPGA-Based Classification of Network Application Protocols. APPLIED SOFT COMPUTING, 2016, vol. 38, no. 1, p. 933-941. ISSN: 1568-4946.
  Detail | WWW

• 2015

  KOŠAŘ, V.; KOŘENEK, J. Towards Efficient Field Programmeable Pattern Matching Array. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 1-8. ISBN: 978-1-4673-8035-5.
  Detail

• 2014

  KOŠAŘ, V.; KOŘENEK, J. On NFA-Split Architecture Optimizations. In 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Warsaw: IEEE Computer Society, 2014. p. 274-277. ISBN: 978-1-4799-4558-0.
  Detail

  KOŠAŘ, V.; KOŘENEK, J. Multi-Stride NFA-Split Architecture for Regular Expression Matching Using FPGA. Proceedings of the 9th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS s.r.o., 2014. p. 77-88. ISBN: 978-80-214-5022-6.
  Detail | WWW

• 2013

  VIKTORIN, J.; KORČEK, P.; KOŠAŘ, V.; KOŘENEK, J. Framework for Fast Prototyping of Applications running on Reconfigurable Systems on Chip. Proceedings of the 2013 Conference on Design & Architectures for Signal & Image Processing. Cagliari: European Electronic Chips & Systems design Initiative, 2013. p. 355-356. ISBN: 979-10-92279-01-6.
  Detail | WWW

  KOŠAŘ, V. Optimalizace architektury NFA-Split. Počítačové architektury a diagnostika PAD 2013. Plzeň: Západočeská univerzita v Plzni, 2013. p. 81-86. ISBN: 978-80-261-0270-0.
  Detail

  KOŠAŘ, V.; ŽÁDNÍK, M.; KOŘENEK, J. NFA Reduction for Regular Expressions Matching Using FPGA. Proceedings of the 2013 International Conference on Field Programmable Technology. Kyoto: IEEE Computer Society, 2013. p. 338-341. ISBN: 978-1-4799-2199-7.
  Detail | WWW

  KAŠTIL, J.; KOŠAŘ, V.; KOŘENEK, J. Hardware Architecture for the Fast Pattern Matching. 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Brno: IEEE Computer Society, 2013. p. 120-123. ISBN: 978-1-4673-6133-0.
  Detail

• 2012

  KOŘENEK, J.; KORČEK, P.; KOŠAŘ, V.; ŽÁDNÍK, M.; VIKTORIN, J. A New Embedded Platform for Rapid Development of Networking Applications. Proceedings of the 2012 Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2012). Austin: IEEE Computer Society, 2012. p. 81-82. ISBN: 978-1-4503-1684-2.
  Detail | WWW

  KOŠAŘ, V. Využití Redukce NKA pro Vyhledávání Vzorů v FPGA. Počítačové architektury a diagnostika 2012. Milovy: Fakulta informačních technologií ČVUT, 2012. p. 97-102. ISBN: 978-80-01-05106-1.
  Detail

• 2011

  KOŠAŘ, V.; KOŘENEK, J. Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 401-402. ISBN: 978-1-4244-9753-9.
  Detail | WWW

  KORČEK, P.; KOŠAŘ, V.; ŽÁDNÍK, M.; KORANDA, K.; KAŠTOVSKÝ, P. Hacking NetCOPE to run on NetFPGA-10G. Proceedings of the 2011 Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2011). Brooklyn, New York: IEEE Computer Society, 2011. p. 1-2. ISBN: 978-0-7695-4521-9.
  Detail | WWW

  KOŠAŘ, V. Redukce Zabraných Zdrojů FPGA pro Vyhledávání Vzorů Popsaných Regulárními Výrazy. Počítačové architektury a diagnostika 2011. Stará Lesná: Fakulta informatiky a informačních technologií Slovenská technická univerzita v Bratislavě, 2011. p. 1-6. ISBN: 978-80-227-3552-0.
  Detail

  PUŠ, V.; TOBOLA, J.; KAŠTIL, J.; KOŠAŘ, V.; KOŘENEK, J. Netbench - the Framework for Evaluation of Packet Processing Algorithms. Proceedings of the 7th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. New York: IEEE Computer Society, 2011. p. 95-96. ISBN: 978-0-7695-4521-9.
  Detail | WWW

• 2010

  KOŘENEK, J.; KOŠAŘ, V. Architektura NFA Split pro rychlé hledání regulárních výrazů. Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. La Jolla: Association for Computing Machinery, 2010. p. 1-2. ISBN: 978-1-4503-0379-8.
  Detail

  KOŘENEK, J.; KOŠAŘ, V. Efficient Mapping of Nondeterministic Automata to FPGA for Fast Regular Expression Matching. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Vienna: IEEE Computer Society, 2010. p. 54-59. ISBN: 978-1-4244-6610-8.
  Detail

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