Czech Science Foundation - Standardní projekty

- whole funder (1995-01-01 - 1997-12-31)

GA102/95/1334

Czech

Cigánek Petr, Ing. - fellow researcher
Drábek Vladimír, doc. Ing., CSc. - fellow researcher
Eysselt Miloš, Ing., CSc. - fellow researcher
Fučík Otto, doc. Dr. Ing. - fellow researcher
Kotásek Zdeněk, doc. Ing., CSc. - fellow researcher
Schwarz Josef, doc. Ing., CSc. - fellow researcher
Sllame M. Azeddien, Ing. - fellow researcher
Zendulka Jaroslav, doc. Ing., CSc. - fellow researcher
Dvořák Václav, prof. Ing., DrSc. - principal person responsible

Faculty of Electrical Engineering and Communication
- beneficiary (2004-05-13 - not assigned)

ZENDULKA, J. Program for demonstration of scheduling and allocation in high-level synthesis. Proceedings of EDS'96. Brno: Brno University of Technology, 1996. p. 382-385. ISBN: 80-214-0767-8.
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DVOŘÁK, V.; ŠUSTR, J. A synthesis of suboptimal decision diagrams. Computer and Artificial Intelligence, 1995, vol. 14, no. 1, p. 93-103. ISSN: 0232-0274.
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ZENDULKA, J. The use of VHDL in designing with gate arrays. Proceedings of MOSIS'96, Volume 2. Krnov: 1996. p. 142-147. ISBN: 80-85988-03-8.
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ZENDULKA, J. Program for demonstration of ROBDD's. Proceedings of EDS'95. Brno: Brno University of Technology, 1995. p. 201-202.
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KOTÁSEK, Z.; ZBOŘIL, F. RT Level Testability Analysis to Reduce Test Application Time. Proceedings of the EUROMICRO 97. Budapest: unknown, 1997. p. 104-111. ISBN: 0-8186-8129-2.
Detail

KOTÁSEK, Z.; ZBOŘIL, F. RT Level Testability Analysis In PROLOG Enviroment. Proceedings of the DDECS'97. Ostrava: 1997. p. 47-52. ISBN: 80-85988-19-4.
Detail

HLAVIČKA, J.; KOTÁSEK, Z.; ZBOŘIL, F. Test Overhead Reduction through RT Level Testability Analysis. Proceedings of the IEEE ETW 1997. Cagliary: unknown, 1997. p. 43-47.
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SCHWARZ, J. Educational fuzzy development system. Proceedings of Conference MOSIS '97. Hradec nad Moravicí: 1997. p. 233-238. ISBN: 80-85988-16-X.
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SCHWARZ, J. Experimental study on parallel genetic algorithm for placement optimalization. Mendel '97. Brno: Faculty of Mechanical Engineering BUT, 1997. p. 148-153. ISBN: 80-214-0884-7.
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SCHWARZ, J. Motorola microcontroller as the platform for fuzzy application. Proceedings of CSS '96. Brno: unknown, 1996. p. 239-242. ISBN: 80-214-0768-9.
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SCHWARZ, J. The FIDE system flexibility in the process of the fuzzy system design. Proceedings of MOSIS'96. Krnov: 1996. s. 82-87. ISBN: 80-85988-02-X.
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KOTÁSEK, Z. RT Level Element Classification. Proceedings of the DDECS 97. Soláň: unknown, 1997. p. 41-46. ISBN: 80-85988-19-4.
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HLAVIČKA, J.; KOTÁSEK, P.; KOTÁSEK, Z. RT Level Test Scheduling Procedure. Proceedings on Design Metodologies for Microelectronics. Smolenice: Slovak Academy of Science, 1995. p. 264-271.
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EYSSELT, M. A Covering of the Boolean Functions. Proceedings of the XIXth International Workshop ASIS 1997. Krnov, September 16-18: unknown, 1997. p. 103-108. ISBN: 80-85988-20-8.
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EYSSELT, M. The Design of the Factored TANT and TONT Networks. Proceedings of the 31st Spring International Conference MOSIS'97. April 28-30, Hradec nad Moravicí: unknown, 1997. p. 177-182. ISBN: 80-85988-18-6.
Detail

EYSSELT, M. The Perfect Microinstruction Pipeline with Microprogram Counters. Proceedings of the Scientific Conference with International Participation ELECTRONIC COMPUTERS & INFORMATICS. September 26-27, Košice-Herĺany: unknown, 1996. p. 176-181.
Detail

EYSSELT, M. A Rounding Problem of the Integers. Proceedings of the AMSE Scientific Conference on Communications, Signals and Systems CSS'96. September 10-12, Brno: Faculty of Electrical Engineering and Computer Science BUT, 1996. p. 55-58. ISBN: 80-214-0768-9.
Detail

EYSSELT, M. The Petri Net Machines for Signed Digit Recodings. Proceedings of the XVIIIth International Workshop Advanced Simulation of Systems ASS 1996. September 17-19, Zábřeh na Moravě: unknown, 1996. p. 136-141. ISBN: 80-85988-10-0.
Detail

EYSSELT, M. The Comparison of Three One-Bit-at-a-Time Two's Complement Multiplication Methods. Proceedings of the AMSE Scientific Conference on Communications, Signals and Systems CSS'96. September 10-12, Brno: Faculty of Electrical Engineering and Computer Science BUT, 1996. p. 41-44. ISBN: 80-214-0768-9.
Detail

EYSSELT, M. The Contribution to a Standard Fixed-Point Division. Proceedings of the AMSE Scientific Conference on Communications, Signals and Systems CSS'96. September 10-12, Brno: Faculty of Electrical Engineering and Computer Science BUT, 1996. p. 37-40. ISBN: 80-214-0768-9.
Detail

EYSSELT, M. The Finite-State Machines Simplified Booth Recodings. Proceedings of the 30th Spring International Conference Modelling and Simulation MOSIS'96. April 23-25, Krnov: unknown, 1996. p. 130-135. ISBN: 80-85988-03-8.
Detail

DVOŘÁK, V.; SLLAME, A. An FPGA-Based Systolic Serial Multiplier. Proceedings of the 5th Electronic Devices and Systems Conference 1998. Brno: unknown, 1998. p. 394-397. ISBN: 80-214-1198-8.
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DVOŘÁK, V. Construction of optimum OBDDs using parallel genetic approach. Proceedings of the 2nd International Conference MENDEL' 96. Brno: unknown, 1996. p. 221-222. ISBN: 80-214-0769-7.
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DVOŘÁK, V. Decomposition techniques for look-up table based FPGA design. Proc. of the Workshop on Design Methodologies for Microelectronics. Smolenice: Slovak Academy of Science, 1995. p. 249-250.
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DVOŘÁK, V. Logic decomposition into LUT/MUX-based logic blocks. Proceedings of the 7th School VLSI and ASIC Design. Baligrod-Bystre: unknown, 1995. p. 37-56. ISBN: 83-900859-3-3.
Detail

ZENDULKA, J. Tools for designing with Xilinx FPGAs. Proceedings of EDS'96. Brno: Brno University of Technology, 1996. p. 15-18. ISBN: 80-214-0767-8.
Detail

http://www.fee.vutbr.cz/UIVT/research/ca/flexag1.html