Project detail

Design and hardware implementation of a patent-invention machine

Duration: 01.01.2007 — 31.12.2009

Funding resources

Czech Science Foundation - Standardní projekty

- whole funder (2007-01-01 - 2009-12-31)

On the project

Tento projekt základního výzkumu se zabývá novým přístupem k návrhu a implementaci inteligentních strojů. Cílem projektu je navrhnout a implementovat zařízení umožňující automaticky generovat inovativní řešení, která budou schopna soutěžit s výtvory kreativního návrháře a budou patentovatelná. Toto zařízení bude založeno na implementaci systému pro genetické programování akcelerované s využitím programovatelného hradlového pole, které na jednom čipu integruje jak rekonfigurovatelnou logiku tak i procesory PowerPC. Pomocí tohoto zařízení budou automaticky generována patentovatelná řešení v oblastech návrhu číslicových obvodů, plánování, zpracování obrazů, predikce, návrhu molekul apod. Protože toto zařízení bude zhotoveno jako relativně malý vestavěný systém, bude ho možné využít pro generování inteligentních řešení těch problémů, které dynamicky vznikají v reálných aplikacích, např. v mobilních systémech, adaptivních dopravních kontrolérech, robotech apod. Jedná se o multidisciplinární projekt umělé inteligence a různých vědeckých a inženýrských oborů.

Description in English
This basic research project deals with a new approach to the design and implementation of intelligent machines. The aim of this project is to design and implement a machine that will be able to automatically generate human-competitive and patentable inventions. This machine will be based on a genetic programming system accelerated using a field programmable gate array that integrates reconfigurable logic as well as PowerPC processors on a single chip. The machine will be utilized to produce human-competitive and patentable inventions in areas of digital circuit design, scheduling, image processing, predicting, molecular design etc. As this machine will be available as a relatively small embedded device it can be utilized to generate intelligent solutions to the dynamically emerging problems in real-world applications, e.g. in mobile systems, adaptive traffic controllers, robots etc. This is a multidisciplinary project of artificial intelligence and various scientific and engineering fields.

Keywords
evoluční návrh, programovatelné hradlové pole, patent

Key words in English
evolutionary design, field programmable gate array, patent

Mark

GA102/07/0850

Default language

Czech

People responsible

Units

Department of Computer Systems
- co-beneficiary (2007-01-01 - 2009-12-31)

Results

JAROŠ, J. Optimalizace kolektivních komunikací na wormhole propojovacích sítích. Sborník příspěvků semináře Počítačové architektury a diagnostika pro studenty doktorského studia. Plzeň: Západočeská univerzita v Plzni, 2007. s. 93-98. ISBN: 987-80-7043-605-9.
Detail

SLANÝ, K.; DVOŘÁK, V. Evolutionary Designed Branch Predictors. 13th International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering BUT, 2007. p. 18-23. ISBN: 978-80-214-3473-8.
Detail

DVOŘÁK, V. Communication Performance of Mesh- and Ring-Based NoCs. Proceedings of the 7th Int. Conference on Networking. New York: IEEE Computer Society, 2008. p. 156-161. ISBN: 978-0-7695-3106-9.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Novel Hardware Implementation of Adaptive Median Filters. In Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. p. 110-115. ISBN: 978-1-4244-2276-0.
Detail

DVOŘÁK, V. Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software. Proceedings of 14th Annual IEEE International Conference and Workshops on the Engineering of Computer-Based Systems. Los Alamitos: IEEE Computer Society, 2007. p. 178-185. ISBN: 0-7695-2772-8.
Detail

DVOŘÁK, V.; JAROŠ, J.; OHLÍDAL, M. Optimum Topology-Aware Scheduling of Collective Communications. In Proceedings of The Sixth International Conference on Networking. New York: IEEE Computer Society, 2007. p. 1-6. ISBN: 0-7695-2805-8.
Detail

DVOŘÁK, V. Space-Time Trade-offs in SW Evaluation of Boolean Functions. Proceedings of The Second International Conference on Systems. New York: IEEE Computer Society, 2007. p. 344-349. ISBN: 0-7695-2807-4.
Detail

SEKANINA, L. Vztah mezi abstraktním a fyzickým výpočtem v kontextu evolučního návrhu. Kognice a umělý život VII. Opava: Slezská univerzita v Opavě, 2007. s. 305-310. ISBN: 9788072484126.
Detail

JAROŠ, J.; OHLÍDAL, M.; DVOŘÁK, V. An Evolutionary Approach to Collective Communication Scheduling. In 2007 Genetic and Evolutionary Computation Conference. Volume II. New York: Association for Computing Machinery, 2007. p. 2037-2044. ISBN: 978-1-59593-697-4.
Detail

SCHWARZ, J.; JAROŠ, J.; OČENÁŠEK, J. Migration of Probabilistic Models for Island-Based Bivariate EDA Algorithm. In 2007 Genetic and Evolutionary Computational Conference. Volume I. New York: Association for Computing Machinery, 2007. p. 631-631. ISBN: 978-1-59593-697-4.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Evaluation of a New Platform For Image Filter Evolution. Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2007. p. 577-584. ISBN: 076952866X.
Detail

JAROŠ, J.; SCHWARZ, J. Parallel BMDA with Probability Model Migration. In Proceeding of 2007 IEEE Congress on Evolutionary Computation. Singapore: IEEE Computer Society, 2007. p. 1059-1066. ISBN: 1-4244-1340-0.
Detail

KOBLIHA, M.; SCHWARZ, J. Self-Organizing Migrating Algorithm for Dynamic Problems: An Experimental study. 13th International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering BUT, 2007. p. 24-29. ISBN: 978-80-214-3473-8.
Detail

VAŠÍČEK, Z.; SEKANINA, L. An Area-Efficient Alternative to Adaptive Median Filtering in FPGAs. Proc. of 2007 International Conference on Field Programmable Logic and Applications. Los Alamitos: IEEE Computer Society, 2007. p. 216-221. ISBN: 1424410606.
Detail

DVOŘÁK, V. Implementation of Combinational and Sequential Functions in Embedded Firmware. Proceedings of the 2007 International Conference on Intelligent Pervasive Computing (IPC-07). Los Alamitos, California: IEEE Computer Society, 2007. p. 80-85. ISBN: 978-0-7695-3006-2.
Detail

ČAPKA, L.; VAŠÍČEK, Z. Investigating the Influence of Mutation Operators in Cartesian Genetic Programming. 13th International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering BUT, 2007. p. 43-47. ISBN: 978-80-214-3473-8.
Detail

BIDLO, M.; VAŠÍČEK, Z. Investigating Gate-Level Evolutionary Development of Combinational Multipliers Using Enhanced Cellular Automata-Based Model. Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009. p. 2241-2248. ISBN: 978-1-4244-2958-5.
Detail

BIDLO, M.; VAŠÍČEK, Z. Development of Combinational Circuits Using Non-Uniform Cellular Automata: Initial Results. Genetic and Evolutionary Computation. New York: Association for Computing Machinery, 2009. p. 1839-1840. ISBN: 978-1-60558-325-9.
Detail

BIDLO, M.; VAŠÍČEK, Z. Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits. Proceedings 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. p. 423-430. ISBN: 978-0-7695-3714-6.
Detail

DVOŘÁK, V. Embedded Firmware Development with Multi-Way Branching. Proc. of the 3rd Int. Coference on Systems. New York: IEEE Computer Society, 2008. p. 317-322. ISBN: 978-0-7695-3105-2.
Detail

JAROŠ, J.; DVOŘÁK, V. An Evolutionary Design Technique for Collective Communications on Optimal Diameter-Degree Networks. In 2008 Genetic and Evolutionary Computational Conference GECCO. New York: Association for Computing Machinery, 2008. p. 1539-1546. ISBN: 978-1-60558-131-6.
Detail

DVOŘÁK, V.; MIKUŠEK, P. LUT Cascade-Based Implementations of Allocators. Proc. of the 25th Convention of EEE in Israel. New York: IEEE Computer Society, 2008. p. 85-89. ISBN: 978-1-4244-2482-5.
Detail

MIKUŠEK, P.; DVOŘÁK, V. On Lookup Table Cascade-Based Realizations of Arbiters. 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008. p. 261-261. ISBN: 978-80-7355-082-0.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Reducing the Area on a Chip Using a Bank of Evolved Filters. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2007. p. 222-232. ISBN: 978-3-540-74625-6.
Detail

BIDLO, M. Evolutionary Design of Generic Combinational Multipliers Using Development. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2007. p. 77-88. ISBN: 978-3-540-74625-6.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerators for Cartesian Genetic Programming. Eleventh European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 230-241. ISBN: 978-3-540-78670-2.
Detail

JAROŠ, J. Evolutionary Design of Fault Tolerant Collective Communications. In Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 261-272. ISBN: 978-3-540-85856-0.
Detail

VAŠÍČEK, Z.; ŽÁDNÍK, M.; SEKANINA, L.; TOBOLA, J. On Evolutionary Synthesis of Linear Transforms. Evolvable Systems: From Biology > to > Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 141-152. ISBN: 978-3-540-85856-0.
Detail

SLANÝ, K. Comparison of CGP and Age-Layered CGP Performance in Image Operator Evolution. Genetic Programming, 12th European Conference, EuroGP 2009. Lecture Notes in Computer Science. Lecture Notes in Computer Science. Tübingen: Springer Verlag, 2009. p. 351-361. ISBN: 978-3-642-01180-1. ISSN: 0302-9743.
Detail

MIKUŠEK, P.; DVOŘÁK, V. Heuristic Synthesis of MTBDDs Based On Local Width Minimization. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009. p. 235-235. ISBN: 978-80-87342-04-6.
Detail

MIKUŠEK, P.; DVOŘÁK, V. On Lookup Table Cascade-Based Realizations of Arbiters. 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008. p. 795-802. ISBN: 978-0-7695-3277-6.
Detail

SLANÝ, K. Branch Predictor On-line Evolutionary System. 2008 Genetic and Evolutionary Computation Conference GECCO. New York: Association for Computing Machinery, 2008. p. 1643-1648. ISBN: 978-1-60558-131-6.
Detail

BIDLO, M.; VAŠÍČEK, Z. Gate-Level Evolutionary Development Using Cellular Automata. 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society Press, 2008. p. 11-18. ISBN: 978-0-7695-3166-3.
Detail

JAROŠ, J.; SCHWARZ, J. Evoluční návrh wormhole kolektivních komunikací. Proceedings of Junior Scientist Conference 2008. Vienna: Technische Universität Wien, 2008. s. 111-112. ISBN: 978-3-200-01612-5.
Detail

ŽALOUDEK, L. Sebereplikace ve výpočetních systémech. Počítačové architektury a diagnostika 2008. Liberec: Technická univerzita v Liberci, 2008. s. 131-136. ISBN: 978-80-7372-378-1.
Detail

KOBLIHA, M. Evolutionary Optimization of Dynamic Problems: a Short Survey. 14th International Conference on Soft Computing. Brno: Faculty of Mechanical Engineering, Czech Technical University, 2008. p. 26-31. ISBN: 978-80-214-3675-6.
Detail

JAROŠ, J.; SCHWARZ, J. Parallel BMDA with an Aggregation of Probability Models. In Proceeding of 2009 IEEE Congress on Evolutionary Computation. Trondheim: IEEE Computational Intelligence Society, 2009. p. 1683-1690. ISBN: 978-1-4244-2959-2.
Detail

JAROŠ, J. Evolutionary Optimization of Multistage Interconnection Networks Performance. In Proceeding of Genetic and Evolutionary Computation Conference, GECCO 2009. New York: Association for Computing Machinery, 2009. p. 1537-1544. ISBN: 978-1-60558-325-9.
Detail

SEKANINA, L. Evolvable Hardware: From Applications to Implications for the Theory of Computation. Proc. of the 8th Int. Conference on Unconventional Computation. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2009. p. 24-36. ISBN: 978-3-642-03744-3.
Detail

MIKUŠEK, P. Dekompoziční techniky pro aplikačně specifické systémy. Počítačové architektury a diagnostika 2009. Zlín: Univerzita Tomáše Bati ve Zlíně, 2009. s. 118-123. ISBN: 978-80-7318-847-4.
Detail

SEKANINA, L.; RŮŽIČKA, R.; GAJDA, Z. Polymorphic FIR Filters with Backup Mode Enabling Power Savings. Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. p. 43-50. ISBN: 978-0-7695-3714-6.
Detail

VAŠÍČEK, Z.; BIDLO, M.; SEKANINA, L.; TORRESEN, J.; GLETTE, K.; FURUHOLMEN, M. Evolution of Impulse Bursts Noise Filters. Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2009. p. 27-34. ISBN: 978-0-7695-3714-6.
Detail

MIKUŠEK, P.; DVOŘÁK, V. Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization. 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009. p. 605-608. ISBN: 978-0-7695-3782-5.
Detail

MIKUŠEK, P. Multi-Terminal BDD Synthesis and Applications. Proceedings 19th International Conference on Field Programmable Logic and Applications (FPL). Prague: IEEE Computer Society, 2009. p. 721-722. ISBN: 978-1-4244-3892-1.
Detail

SLANÝ, K. Towards the Automatic Evolutionary Prediction of the FOREX Market Behaviour. Proceedings of the 2009 International Conference on Adaptive and Intelligent Systems. Klagenfurt: IEEE Computer Society, 2009. p. 141-145. ISBN: 978-0-7695-3827-3.
Detail

SLANÝ, K.; SEKANINA, L. Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP. Genetic Programming, 10th European Conference, EuroGP 2007. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2007. p. 311-320. ISBN: 978-3-540-71602-0.
Detail

ŽALOUDEK, L.; SEKANINA, L.; ŠIMEK, V. GPU Accelerators for Evolvable Cellular Automata. Computation World: Future Computing, Service Computation, Adaptive, Content, Cognitive, Patterns. Athens: Institute of Electrical and Electronics Engineers, 2009. p. 533-537. ISBN: 978-0-7695-3862-4.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Efficient Hardware Accelerator for Symbolic Regression Problems. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009. p. 192-199. ISBN: 978-80-87342-04-6.
Detail

ŽALOUDEK, L. Akcelerace evoluce pravidel celulárních automatů na GPU. Počítačové architektury a diagnostika 2009. Zlín: Univerzita Tomáše Bati ve Zlíně, 2009. s. 173-178. ISBN: 978-80-7318-847-4.
Detail

GAJDA, Z. Návrh a optimalizace polymorfních obvodů. Počítačová architektura a Diagnostika 2009. Zlín: Univerzita Tomáše Bati ve Zlíně, 2009. s. 63-67. ISBN: 978-80-7318-847-4.
Detail

VAŠÍČEK, Z.; SEKANINA, L. An Evolvable Hardware System in Xilinx Virtex II Pro FPGA. International Journal of Innovative Computing and Applications, 2007, vol. 1, no. 1, p. 63-73. ISSN: 1751-648X.
Detail

DVOŘÁK, V. LUT Cascade-Based Architectures for High Productivity Embedded Systems. International Review on Computers and Software, 2007, vol. 2, no. 4, p. 357-365. ISSN: 1828-600X.
Detail

DVOŘÁK, V. Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware. Journal of Software, 2007, vol. 2, no. 5, p. 52-63. ISSN: 1796-217X.
Detail

SEKANINA, L. Evolved Computing Devices and the Implementation Problem. MINDS AND MACHINES, 2007, vol. 17, no. 3, p. 311-329. ISSN: 0924-6495.
Detail

DVOŘÁK, V.; MIKUŠEK, P. Optimalizace firmware pro vestavěné logcké řízení. Programmable devices and systems, 2009, roč. 2009, č. 1, s. 109-114. ISSN: 1474-6670.
Detail

DVOŘÁK, V. Implementation of Combinational and Sequential Functions in Embedded Firmware. International Journal of Software Engineering and Its Applications, 2008, vol. 2, no. 1, p. 43-54. ISSN: 1738-9984.
Detail

PEČENKA, T.; SEKANINA, L.; KOTÁSEK, Z. Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, vol. 13, no. 3, p. 1-21. ISSN: 1084-4309.
Detail

BIDLO, M.; ŠKARVADA, J. Instruction-based development: From evolution to generic structures of digital circuits. International Journal of Knowledge-Based and Intelligent Engineering Systems, 2008, vol. 12, no. 3, p. 221-236. ISSN: 1327-2314.
Detail

VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics, 2010, vol. 29, no. 6, p. 1359-1371. ISSN: 1335-9150.
Detail

SEKANINA, L.; MARTÍNEK, T. Evolving Image Operators Directly in Hardware. In Genetic and Evolutionary Computation for Image Processing and Analysis. EURASIP Book Series on Signal Processing and Communications, Volume 8. New York: Hindawi Publishing Corporation, 2007. p. 93-112. ISBN: 978-977-454-001-1.
Detail

SCHWARZ, J.; JAROŠ, J. Parallel Bivariate Marginal Distribution Algorithm with Probability Model Migration. In Linkage in Evolutionary Computation. LNSC, Studies in Computational Intelligence Vol. 157. Berlin / Heidelberg: Springer Verlag, 2008. p. 3-23. ISBN: 978-3-540-85067-0.
Detail

JAROŠ, J. Evolutionary Design of Collective Communications on Wormhole Networks. Brno: Publishing house of Brno University of Technology VUTIUM, 2010. 183 p. ISBN: 978-80-214-4208-5.
Detail

SEKANINA, L.; VAŠÍČEK, Z.; RŮŽIČKA, R.; BIDLO, M.; JAROŠ, J.; ŠVENDA, P. Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům. Edice Gerstner. Edice Gerstner. Praha: Nakladatelství Academia, 2009. 328 s. ISBN: 978-80-200-1729-1.
Detail

HORNBY, G.; SEKANINA, L.; HADDOW, P. Proceedings of Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 0-0. ISBN: 978-3-540-85856-0.
Detail

SEKANINA, L. Evolvable hardware. In Handbook of Natural Computing. Berlin: Springer Verlag, 2012. p. 1657-1705. ISBN: 978-3-540-92909-3.
Detail

SEKANINA, L.; VAŠÍČEK, Z.; Vysoké učení technické v Brně, Fakulta informačních technologií: Nelineární obrazový filtr. UV020017, užitný vzor. Praha (2009)
Detail

VAŠÍČEK, Z.; SEKANINA, L.: EHWFILTER; Hardware Accelerator for Evolutionary Image Filters Design. Ústav počítačových systémů, Fakulta informačních technologií VUT v Brně, Božetěchova 2, 612 66 Brno, http://www.fit.vutbr.cz/units/UPSY/. URL: https://www.fit.vut.cz/research/product/94/. (funkční vzorek)
Detail

VAŠÍČEK, Z.; SEKANINA, L.: Tools4CGP; Nástroje pro kartézské genetické programování. Software je ke stažení z URL: http://www.fit.vutbr.cz/~vasicek/cgp/tools. URL: https://www.fit.vut.cz/research/product/61/. (software)
Detail

PEČENKA, T.; KOTÁSEK, Z.: Cirgen; RTL benchmark circuit generator. Software je společně se sadou vytvořených testovacích obvodů ke stažení z URL: http://www.fit.vutbr.cz/~pecenka/cirgen/. URL: https://www.fit.vut.cz/research/product/55/. (software)
Detail

ŠIMEK, V.; RŮŽIČKA, R.; SEKANINA, L.; VAŠÍČEK, Z.: REPOMOkit; REPOMOkit - univerzální vývojová platforma pro polymorfní elektroniku. Ústav počítačových systémů, Fakulta informačních technologií VUT v Brně. URL: https://www.fit.vut.cz/research/product/93/. (funkční vzorek)
Detail

Responsibility: Sekanina Lukáš, prof. Ing., Ph.D.

VUT

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Parts

Design and hardware implementation of a patent-invention machine