Publication detail

Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability

PEČENKA, T. SEKANINA, L. KOTÁSEK, Z.

Original Title

Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability

Type

journal article - other

Language

English

Original Abstract

This article presents a new real-world application of evolutionary computing in the area of digital-circuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits.

Keywords

evolutionary algorithm, digital circuit, testability analysis

Authors

PEČENKA, T.; SEKANINA, L.; KOTÁSEK, Z.

RIV year

2008

Released

23. 7. 2008

ISBN

1084-4309

Periodical

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS

Year of study

13

Number

3

State

United States of America

Pages from

1

Pages to

21

Pages count

21

URL

https://www.fit.vut.cz/research/publication/8653/

BibTex

@article{BUT48172,
  author="Tomáš {Pečenka} and Lukáš {Sekanina} and Zdeněk {Kotásek}",
  title="Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability",
  journal="ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS",
  year="2008",
  volume="13",
  number="3",
  pages="1--21",
  issn="1084-4309",
  url="https://www.fit.vut.cz/research/publication/8653/"
}

Documents

todaes08.pdf