Project detail
Designing and exploiting libraries of approximate circuits
Duration: 1.1.2019 — 31.12.2021
Funding resources
Grantová agentura České republiky - Standardní projekty
On the project
Aproximativní obvody jsou stavební bloky složitých systémů na čipu, které dokáží přizpůsobit kvalitu produkovaného výstupu dostupnému příkonu. Návrh aproximativního obvodu, který bude vykazovat dobrý kompromis mezi chybou a dalšími parametry, je stále návrhářskou výzvou. Navrhujeme zkrátit dobu návrhu a zvýšit složitost obvodů, které jsou rutinně aproximovány, tím, že (i) vytvoříme obsáhlou knihovnu elementárních aproximativních obvodů a (ii) zavedeme vhodné kompoziční algoritmy využívající elementárních obvody dostupné v knihovně. Sestavení složitého aproximativního obvodu z elementárních aproximativních obvodů je obtížný problém, protože není obecně zřejmé, jak provést (de)kompozici a jak se budou chyby elementárních aproximativních obvodů projevovat na globální úrovni. Projekt směřuje k následujícím přínosům: (i) účinné deterministické a evoluční kompoziční algoritmy pro návrh aproximativních obvodů, (2) knihovna obsahující přes 1 milion aproximativních obvodů a (3) získání nových znalostí o aproximativních obvodech analýzou dat z knihovny.
Description in English
Approximate circuits are building blocks of complex systems on a chip that can
exchange the quality of processing for power consumption reduction. The design of
an approximate circuit showing good tradeoffs between the error and other
parameters is still a challenging task. We propose to reduce the design time and
increase the complexity of circuits that can routinely be approximated by (i)
developing a comprehensive library of elementary approximate circuits and (ii)
introducing suitable compositional schemes exploiting the elementary circuits
available in the library. Assembling a complex approximate circuit from
approximate sub-circuits is a challenging problem as it is, in general, unclear
how to perform the (de)composition and how the errors of these sub-circuits
manifest at the global level. The project seeks the following contributions: (1)
efficient deterministic and evolutionary compositional algorithms for approximate
circuit design, (2) a library containing over 1 million approximate circuits, and
(3) new knowledge about approximate circuits by analyzing the library.
Keywords
aproximativní obvod, počítačem podporovaný návrh, genetické programování,
evoluční hardware, knihovna číslicových obvodů
Key words in English
approximate circuit, computer aided design, genetic programming, evolvable
hardware, digital circuit library
Mark
GA19-10137S
Default language
Czech
People responsible
Sekanina Lukáš, prof. Ing., Ph.D. - principal person responsible
Bidlo Michal, doc. Ing., Ph.D. - fellow researcher
Drahošová Michaela, Ing., Ph.D. - fellow researcher
Husa Jakub, Ing., Ph.D. - fellow researcher
Chlebík Jakub, Ing. - fellow researcher
Klhůfek Jan, Ing. - fellow researcher
Kocnová Jitka, Ing., Ph.D. - fellow researcher
Mrázek Vojtěch, Ing., Ph.D. - fellow researcher
Piňos Michal, Ing. - fellow researcher
Strnadel Josef, Ing., Ph.D. - fellow researcher
Vašíček Zdeněk, doc. Ing., Ph.D. - fellow researcher
Units
Department of Computer Systems
- responsible department (5.4.2018 - not assigned)
Evolvable Hardware Research Group
- internal (5.4.2018 - 31.12.2021)
Department of Computer Systems
- beneficiary (5.4.2018 - 31.12.2021)
Results
BIDLO, M. Evolution of Approximate Functions for Image Thresholding. In IEEE Symposium Series on Computational Intelligence (IEEE SSCI). Los Alamos: IEEE Computer Society, 2021. p. 1-6. ISBN: 978-1-7281-9048-8.
Detail
SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Inexact Arithmetic Operators. In Approximate Computing Techniques. Cham: Springer International Publishing, 2022. p. 81-107. ISBN: 978-3-030-94704-0.
Detail
STRNADEL, J. Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. In Proceedings of 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Prague: Institute of Electrical and Electronics Engineers, 2022. p. 88-93. ISBN: 978-1-6654-9431-1.
Detail
HODAŇ, D.; MRÁZEK, V.; VAŠÍČEK, Z. Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genetic Programming and Evolvable Machines, 2021, vol. 22, no. 4, p. 539-572. ISSN: 1389-2576.
Detail
CHLEBÍK, J.; JAROŠ, J. Distributed Evolutionary Design of High Intensity Focused Ultrasound Treatment Plans. In IEEE International Conference on Systems, Man and Cybernetics. Melbourne: IEEE Circuits and Systems Society, 2021. p. 2203-2208. ISBN: 978-1-6654-4207-7.
Detail
KOCNOVÁ, J.; VAŠÍČEK, Z. Resynthesis of logic circuits using machine learning and reconvergent paths. In 2021 24th Euromicro Conference on Digital System Design (DSD). Palermo: Institute of Electrical and Electronics Engineers, 2021. p. 69-76. ISBN: 978-1-6654-2704-3.
Detail
STRNADEL, J. Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. In Proceedings of 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Vienna: Institute of Electrical and Electronics Engineers, 2021. p. 111-114. ISBN: 978-1-6654-3595-6.
Detail
MARCHISIO, A.; MRÁZEK, V.; HANIF, M.; SHAFIQUE, M. FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Trans. on VLSI Systems., 2021, vol. 29, no. 4, p. 716-729. ISSN: 1063-8210.
Detail
VAŠÍČEK, Z. Synthesis of approximate circuits for LUT-based FPGAs. In 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Vienna: IEEE Computer Society, 2021. p. 17-22. ISBN: 978-1-6654-3595-6.
Detail
MARCHISIO, A.; MRÁZEK, V.; HANIF, M.; SHAFIQUE, M. DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, vol. 40, no. 9, p. 1768-1781. ISSN: 1937-4151.
Detail
HUSA, J.; SEKANINA, L. Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. In 2020 IEEE Congress on Evolutionary Computation (CEC). Los Alamitos: IEEE Computational Intelligence Society, 2020. p. 1-8. ISBN: 978-1-7281-6929-3.
Detail
MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z. Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2020, vol. 10, no. 4, p. 406-418. ISSN: 2156-3357.
Detail
KOCNOVÁ, J.; VAŠÍČEK, Z. EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits. Genetic Programming and Evolvable Machines, 2020, vol. 21, no. 3, p. 287-319. ISSN: 1389-2576.
Detail
BOSIO, A.; DI CARLO, S.; GIRARD, P.; SANCHEZ, E.; SAVINO, A.; SEKANINA, L.; TRAIOLA, M.; VAŠÍČEK, Z.; VIRAZEL, A. Design, Verification, Test and In-Field Implications of Approximate Computing Systems. In 25th IEEE European Test Symposium. Los Alamitos: Institute of Electrical and Electronics Engineers, 2020. p. 1-10. ISBN: 978-1-7281-4312-5.
Detail
PRABAKARAN, B.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. In 2020 57th ACM/IEEE Design Automation Conference (DAC). San Francisco: Institute of Electrical and Electronics Engineers, 2020. p. 1-6. ISBN: 978-1-4503-6725-7.
Detail
BIDLO, M. Evolution of Cellular Automata with Conditionally Matching Rules for Image Filtering. In 2020 IEEE Congress on Evolutionary Computation (CEC). Los Alamitos: IEEE Computational Intelligence Society, 2020. p. 1-8. ISBN: 978-1-7281-6929-3.
Detail
MRÁZEK, V.; SEKANINA, L.; VAŠÍČEK, Z. Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. In 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems. Genoa: Institute of Electrical and Electronics Engineers, 2020. p. 243-247. ISBN: 978-1-7281-4922-6.
Detail
VAVERKA, F.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: Institute of Electrical and Electronics Engineers, 2020. p. 294-297. ISBN: 978-3-9819263-4-7.
Detail
MARCHISIO, A.; MRÁZEK, V.; HANIF, M.; SHAFIQUE, M. ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Grenoble: Institute of Electrical and Electronics Engineers, 2020. p. 1205-1210. ISBN: 978-3-9819263-4-7.
Detail
MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.: EvoApproxLib; EvoApproxLib - a comprehensive collection of low-level approximate implementations of arithmetic operations. Implementace a všechny dodatečné informace se nacházejí na https://ehw.fit.vutbr.cz/evoapproxlib/ a na https://github.com/ehw-fit/evoapproxlib/. URL: https://www.fit.vut.cz/research/product/632/. (software)
Detail
Responsibility: Sekanina Lukáš, prof. Ing., Ph.D.