Project detail

Automated design of hardware accelerators for resource-aware machine learning

Duration: 01.01.2021 — 31.12.2023

Funding resources

Czech Science Foundation - Standardní projekty

- part funder (2021-01-01 - 2023-12-31)

On the project

Strojové učení, zejména technologie využívající hluboké neuronové sítě (DNN), v mnoha oblastech dosahuje a přesahuje schopnosti kvalifikovaných expertů. Významné využití metod strojového učení je očekáváno v zařízených napájených bateriemi, kde je kladen důraz na redukci energie a zdrojů na čipu. Současný přístup k návrhu DNN je založen na polo-automatizovaném zjednodušování DNN, jenž byla původně vytvořena expertem, který ale jen částečně mohl ovlivnit hardwarové aspekty její implementace. Cílem projektu je vytvořit a vyhodnotit metodologii umožňující vysoce automatizovaný návrh obvodových akcelerátorů DNN (a dalších metod strojového učení), které budou vykazovat vynikající kompromis mezi kvalitou výstupu, spotřebovanou energií a zdroji na čipu. Navržený přístup je založen na evolučním návrhu implementací DNN (a dalších vybraných metod strojového učení), který bude zohledňovat cílovou hardwarovou platformu. Metoda bude vyhodnocena na standardních úlohách (zejména z oblasti klasifikace obrázků) a také na automatické detekci Parkinsonovy choroby.

Description in English
Machine learning (ML), particularly the technology based on deep neural networks (DNNs), has already reached and overcome human-level capabilities in many domains. A significant future use of trained ML models is expected in battery powered devices, where the major constraints are energy and the amount of resources available on a chip. The current approach to the DNN design is based on semi-automated simplifying of a network which is created by a human expert who could only partly reflect all hardware implementation aspects. In this project, the aim is to propose and evaluate a methodology for the highly automated design of hardware accelerators of DNNs (and other selected ML methods) that show excellent trade-offs between the output quality, energy and resources used on a single chip. Our approach is based on evolutionary design of such implementations of DNNs (and other ML systems) that reflect a target hardware platform. The proposed method will be evaluated on standard benchmark problems such as image classification and on automated assessment of Parkinsons disease.

Keywords
evoluční algoritmus, hluboká neuronová síť, strojové učení, akcelerátor, číslicový obvod, příkon, evoluční hardware

Key words in English
evolutionary algorithm, deep neural network, machine learning, accelerator, digital circuit, power consumption, evolvable hardware

Mark

GA21-13001S

Default language

Czech

People responsible

Drahošová Michaela, Ing., Ph.D. - fellow researcher
Hurta Martin, Ing. - fellow researcher
Matoušek Jiří, Ing., Ph.D. - fellow researcher
Mrázek Vojtěch, Ing., Ph.D. - fellow researcher
Piňos Michal, Ing. - fellow researcher
Vašíček Zdeněk, doc. Ing., Ph.D. - fellow researcher
Žufan Petr, Ing. - fellow researcher
Sekanina Lukáš, prof. Ing., Ph.D. - principal person responsible

Units

Department of Computer Systems
- beneficiary (2020-04-23 - 2023-12-31)

Results

PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Evolutionary Neural Architecture Search Supporting Approximate Multipliers. In Genetic Programming, 24th European Conference, EuroGP 2021. Lecture Notes in Computer Science, vol 12691. Seville: Springer Nature Switzerland AG, 2021. p. 82-97. ISBN: 978-3-030-72812-0.
Detail

HUSA, J.; SEKANINA, L. Semantic Mutation Operator for Fast and Efficient Design of Bent Boolean Functions. Genetic Programming and Evolvable Machines, 2024, vol. 25, no. 3, p. 1-32. ISSN: 1389-2576.
Detail

HANIF, M.; MRÁZEK, V.; SHAFIQUE, M. Approximate Computing Architectures. In Handbook of Computer Architecture. Handbook of Computer Architecture. Singapore: Springer Nature Singapore, 2022. p. 1-41. ISBN: 978-981-1564-01-7.
Detail

SEKANINA, L. Neural Architecture Search and Hardware Accelerator Co-Search: A Survey. IEEE Access, 2021, vol. 9, no. 9, p. 151337-151362. ISSN: 2169-3536.
Detail

HURTA, M.; DRAHOŠOVÁ, M.; SEKANINA, L.; SMITH, S.; ALTY, J. Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. In Genetic Programming, 25th European Conference, EuroGP 2022. Lecture Notes in Computer Science. Madrid: Springer Nature Switzerland AG, 2022. p. 85-101. ISBN: 978-3-031-02055-1.
Detail

BOSIO, A.; DI CARLO, S.; GIRARD, P.; RUOSPO, A.; SANCHEZ, E.; SAVINO, A.; SEKANINA, L.; TRAIOLA, M.; VAŠÍČEK, Z.; VIRAZEL, A. Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated Circuits. In Approximate Computing Techniques. Cham: Springer International Publishing, 2022. p. 349-385. ISBN: 978-3-030-94704-0.
Detail

HURTA, M.; DRAHOŠOVÁ, M.; MRÁZEK, V. Evolutionary Design of Reduced Precision Preprocessor for Levodopa-Induced Dyskinesia Classifier. In Parallel Problem Solving from Nature - PPSN XVII. Lecture Notes in Computer Science. Dortmund: Springer Nature Switzerland AG, 2022. p. 491-504. ISBN: 978-3-031-14713-5.
Detail

PIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Evolutionary Approximation and Neural Architecture Search. Genetic Programming and Evolvable Machines, 2022, vol. 23, no. 3, p. 351-374. ISSN: 1389-2576.
Detail

PIŇOS, M.; MRÁZEK, V.; VAVERKA, F.; VAŠÍČEK, Z.; SEKANINA, L. Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023, vol. 13, no. 1, p. 212-224. ISSN: 2156-3357.
Detail

MRÁZEK, V. Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial). In Proceedings of International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '23). Tallinn: Institute of Electrical and Electronics Engineers, 2023. p. 91-92. ISBN: 979-8-3503-3277-3.
Detail

HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallinn: Institute of Electrical and Electronics Engineers, 2023. p. 155-160. ISBN: 979-8-3503-3277-3.
Detail

HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). Antwerp: Institute of Electrical and Electronics Engineers, 2023. p. 1-2. ISBN: 978-3-9819263-7-8.
Detail

LOJDA, J.; PÁNEK, R.; SEKANINA, L.; KOTÁSEK, Z. Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs. Microelectronics Reliability, 2023, vol. 2023, no. 144, p. 1-16. ISSN: 0026-2714.
Detail

JŮZA, T.; SEKANINA, L. GPAM: Genetic Programming with Associative Memory. In 26th European Conference on Genetic Programming (EuroGP) Held as Part of EvoStar. Lecture Notes in Computer Science. LNCS. Cham: Springer Nature Switzerland AG, 2023. p. 68-83. ISBN: 978-3-031-29572-0. ISSN: 0302-9743.
Detail

MRÁZEK, V.; JAWED, S.; ARIF, M.; MALIK, A. Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification. In GECCO 2023 - Proceedings of the 2023 Genetic and Evolutionary Computation Conference. Lisbon: Association for Computing Machinery, 2023. p. 1427-1435. ISBN: 979-8-4007-0119-1.
Detail

QADRI, S.; ARIF, M.; SAEED, M. A Novel Variable Step-Size LMS Algorithm for Decentralized Incremental Distributed Networks. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2023, vol. 41, no. 12, p. 7226-7249. ISSN: 0278-081X.
Detail

CHLEBÍK, J.; JAROŠ, J. Evolutionary Optimization of a Focused Ultrasound Propagation Predictor Neural Network. GECCO 2023 Companion - Proceedings of the 2023 Genetic and Evolutionary Computation Conference Companion. Lisbon: Association for Computing Machinery, 2023. p. 635-638. ISBN: 979-8-4007-0120-7.
Detail

HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. Multi-objective Design of Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. p. 0-0.
Detail

GIACOBINI, M.; PAPPA, G.; VAŠÍČEK, Z. Genetic Programming. LNCS 13986. Cham: Springer Verlag, 2023. p. 0-0. ISBN: 978-3-031-29572-0.
Detail

PRABAKARAN, B.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). San Francisco: Institute of Electrical and Electronics Engineers, 2023. p. 1-9. ISBN: 979-8-3503-1559-2.
Detail

SEKANINA, L.; MRÁZEK, V.; PIŇOS, M. Hardware-Aware Evolutionary Approaches to Deep Neural Networks. In Handbook of Evolutionary Machine Learning. Genetic and Evolutionary Computation. Singapore: Springer Nature Singapore, 2023. p. 367-396. ISBN: 978-981-9938-13-1.
Detail

HUSA, J.; SEKANINA, L. Semantic Mutation Operator for Fast and Efficient Design of Bent Boolean Functions. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. p. 0-0.
Detail

SEKANINA, L. Evolutionary Algorithms in Approximate Computing: A Survey. Journal of Integrated Circuits and Systems, 2021, vol. 16, no. 2, p. 1-12. ISSN: 1872-0234.
Detail

Responsibility: Sekanina Lukáš, prof. Ing., Ph.D.