Project detail

Methodology and tools for digital circuits testability analysis

Duration: 01.01.1998 — 31.03.2006

Funding resources

Czech Science Foundation - Standardní projekty

- whole funder

On the project

Description in English
The goal of the research activities is to develop and implement testability analysis methodology such that the concepts and algorithms could be used in any design environment, to offer an alternative to the full scan approach. It is supposed that the structure of the circuit under analysis will be transformed into a database representing the diagnostic features of the circuit. The applicability will be verified on circuits described in VHDL language and on ISCAS benchmark circuits.

Keywords
diagnostika číslicových obvodů-analýya testovatelnosti

Mark

GA102/98/1463

Default language

Czech

People responsible

Drábek Vladimír, doc. Ing., CSc. - fellow researcher
Fučík Otto, doc. Dr. Ing. - fellow researcher
Zbořil František, doc. Ing., CSc. - fellow researcher
Kotásek Zdeněk, doc. Ing., CSc. - principal person responsible

Units

Faculty of Information Technology
- beneficiary (1998-01-01 - 2000-12-31)

Results

ZBOŘIL, F. VHDL RT Level Parser/Analyser of a Source Code. Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2000. p. 150-155. ISBN: 80-88922-25-9.
Detail

SEKANINA, L.; DRÁBEK, V. Fault Tolerance and Reconfiguration in Cellular Systems. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. p. 134-137. ISBN: 80-968320-3-4.
Detail

ZBOŘIL, F., KOTÁSEK, Z. Nonstandard Automatic Test Pattern Generation Based on Neural Network Theory. In Proceedings of the ECI'98. Herlany, SR: SAV, 1998. p. 75-80. ISBN: 80-88786-94-0.
Detail

SEKANINA, L.; RŮŽIČKA, R. Design of the Special Fast Reconfigurable Chip Using Common FPGA. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. p. 161-168. ISBN: 80-968320-3-4.
Detail

SEKANINA, L.; DRÁBEK, V. Relation Between Fault Tolerance and Reconfiguration in Cellular Systems. 6th IEEE Int. On-Line Testing Workshop. Palma de Mallorca, Spain: IEEE Computer Society Press, 2000. p. 25-30. ISBN: 0-7695-0646-1.
Detail

Responsibility: Kotásek Zdeněk, doc. Ing., CSc.