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MIKA, D. KOTÁSEK, Z. STRNADEL, J.
Original Title
Test Controller Design Based on VHDL Source File Analysis
Type
article in a collection out of WoS and Scopus
Language
English
Original Abstract
In the paper the process of test controller design and synthesis on register transfer level (RTL) is described. The sequence of control, address and data signals together with circuit structure for which the test controller is designed are the input information of the problem. The methodology of transforming an RTL circuit into a labelled directed graph and then into VHDL source code will be presented. The ideas of test controller synthesis based on this information will be explicitly shown.
Keywords
Register Transfer Level, Data Transporter, Data Processor, The Unit Under Analysis
Authors
MIKA, D.; KOTÁSEK, Z.; STRNADEL, J.
RIV year
2002
Released
10. 10. 2002
Publisher
The University of Technology Košice
Location
Letná 42, 040 01 TU Košice
ISBN
80-7099-879-2
Book
Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002
Edition
VIENALA Press, Edition: 55
Pages from
135
Pages to
141
Pages count
6
BibTex
@inproceedings{BUT10249, author="Daniel {Mika} and Zdeněk {Kotásek} and Josef {Strnadel}", title="Test Controller Design Based on VHDL Source File Analysis", booktitle="Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002", year="2002", series="VIENALA Press, Edition: 55", pages="135--141", publisher="The University of Technology Košice", address="Letná 42, 040 01 TU Košice", isbn="80-7099-879-2" }