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MIKA, D. KOTÁSEK, Z. STRNADEL, J.
Originální název
Test Controller Design Based on VHDL Source File Analysis
Typ
článek ve sborníku mimo WoS a Scopus
Jazyk
angličtina
Originální abstrakt
In the paper the process of test controller design and synthesis on register transfer level (RTL) is described. The sequence of control, address and data signals together with circuit structure for which the test controller is designed are the input information of the problem. The methodology of transforming an RTL circuit into a labelled directed graph and then into VHDL source code will be presented. The ideas of test controller synthesis based on this information will be explicitly shown.
Klíčová slova
Register Transfer Level, Data Transporter, Data Processor, The Unit Under Analysis
Autoři
MIKA, D.; KOTÁSEK, Z.; STRNADEL, J.
Rok RIV
2002
Vydáno
10. 10. 2002
Nakladatel
The University of Technology Košice
Místo
Letná 42, 040 01 TU Košice
ISBN
80-7099-879-2
Kniha
Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002
Edice
VIENALA Press, Edition: 55
Strany od
135
Strany do
141
Strany počet
6
BibTex
@inproceedings{BUT10249, author="Daniel {Mika} and Zdeněk {Kotásek} and Josef {Strnadel}", title="Test Controller Design Based on VHDL Source File Analysis", booktitle="Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002", year="2002", series="VIENALA Press, Edition: 55", pages="135--141", publisher="The University of Technology Košice", address="Letná 42, 040 01 TU Košice", isbn="80-7099-879-2" }