Publication detail

Pipelined LFSR Counters

KOLOUCH, J.

Original Title

Pipelined LFSR Counters

Type

conference paper

Language

English

Original Abstract

Fast LFSR counter modifications with the cycle length different than the basic one suitable for implementation in FPGA devices are suggested. Example of VHDL code for 15-bit full cycle counter is given.

Keywords

LFSR counter, FPGA, pipelining, VHDL

Authors

KOLOUCH, J.

RIV year

2004

Released

28. 4. 2004

Location

Bratislava

ISBN

80-227-2017-8

Book

Radioelektronika 2004, Conference Proceedings

Pages from

335

Pages to

338

Pages count

4

BibTex

@inproceedings{BUT10846,
  author="Jaromír {Kolouch}",
  title="Pipelined LFSR Counters",
  booktitle="Radioelektronika 2004, Conference Proceedings",
  year="2004",
  volume="2004",
  pages="4",
  address="Bratislava",
  isbn="80-227-2017-8"
}