Publication detail

Fast Simulation of Pipeline in ASIP simulators

PŘIKRYL, Z.

Original Title

Fast Simulation of Pipeline in ASIP simulators

Type

conference paper

Language

English

Original Abstract

A fast and accurate simulator of the newly designed application specific instruction-set processors is essential during processor development, testing, and verification as well as for software development. Instruction-set simulators are usually used at the early stages of the design. They have good performance, but because of their low accuracy they cannot be used for a detailed pipeline or timing analysis. For this task, cycle-accurate simulators are used. They are of high accuracy since the whole microarchitecture is simulated. But at the same time, the simulation time can be significantly longer than in the case of instruction-set simulators. We present a technique which reduces the simulation time with an acceleration of pipeline simulation. Experimental results show a speed-up during simulation. Moreover, the proposed concept can also be used for hardware realization of application specific instruction-set processors.

Keywords

ASIP, Simulator, Pipeline

Authors

PŘIKRYL, Z.

RIV year

2014

Released

15. 12. 2014

Publisher

IEEE Computer Society

Location

Austin

ISBN

978-0-7695-4000-9

Book

15th International Workshop on Microprocessor Test and Verification

Pages from

1

Pages to

6

Pages count

6

BibTex

@inproceedings{BUT111785,
  author="Zdeněk {Přikryl}",
  title="Fast Simulation of Pipeline in ASIP simulators",
  booktitle="15th International Workshop on Microprocessor Test and Verification",
  year="2014",
  pages="1--6",
  publisher="IEEE Computer Society",
  address="Austin",
  doi="10.1109/MTV.2014.18",
  isbn="978-0-7695-4000-9"
}