Detail publikace

Fast Simulation of Pipeline in ASIP simulators

PŘIKRYL, Z.

Originální název

Fast Simulation of Pipeline in ASIP simulators

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

A fast and accurate simulator of the newly designed application specific instruction-set processors is essential during processor development, testing, and verification as well as for software development. Instruction-set simulators are usually used at the early stages of the design. They have good performance, but because of their low accuracy they cannot be used for a detailed pipeline or timing analysis. For this task, cycle-accurate simulators are used. They are of high accuracy since the whole microarchitecture is simulated. But at the same time, the simulation time can be significantly longer than in the case of instruction-set simulators. We present a technique which reduces the simulation time with an acceleration of pipeline simulation. Experimental results show a speed-up during simulation. Moreover, the proposed concept can also be used for hardware realization of application specific instruction-set processors.

Klíčová slova

ASIP, Simulator, Pipeline

Autoři

PŘIKRYL, Z.

Rok RIV

2014

Vydáno

15. 12. 2014

Nakladatel

IEEE Computer Society

Místo

Austin

ISBN

978-0-7695-4000-9

Kniha

15th International Workshop on Microprocessor Test and Verification

Strany od

1

Strany do

6

Strany počet

6

BibTex

@inproceedings{BUT111785,
  author="Zdeněk {Přikryl}",
  title="Fast Simulation of Pipeline in ASIP simulators",
  booktitle="15th International Workshop on Microprocessor Test and Verification",
  year="2014",
  pages="1--6",
  publisher="IEEE Computer Society",
  address="Austin",
  doi="10.1109/MTV.2014.18",
  isbn="978-0-7695-4000-9"
}