Publication detail

Processor Model for the Instruction Mapping Tool

MEGO, R.

Original Title

Processor Model for the Instruction Mapping Tool

Type

conference paper

Language

English

Original Abstract

This paper describes the model designed for the instruction mapping tool, which can be used for generating the low level assembly code for the digital signal processing algorithms. The model is based on the Very Long Instruction Word architecture. The Texas Instrument TMS320C6678 was the pattern and finally was described with the created model. The paper is showing the parameters of the hardware resources and also the instruction set.

Keywords

Processor model; Instruction mapping; VLIW

Authors

MEGO, R.

Released

10. 2. 2016

Publisher

University Carlos III of Madrid

Location

Madrid

ISBN

978-84-608-6309-0

Book

Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)

Pages from

41

Pages to

44

Pages count

4

URL

http://www.nesus.eu/proceedings

BibTex

@inproceedings{BUT123432,
  author="Roman {Mego}",
  title="Processor Model for the Instruction Mapping Tool",
  booktitle="Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)",
  year="2016",
  pages="41--44",
  publisher="University Carlos III of Madrid",
  address="Madrid",
  isbn="978-84-608-6309-0",
  url="http://www.nesus.eu/proceedings"
}