Detail publikace

Processor Model for the Instruction Mapping Tool

MEGO, R.

Originální název

Processor Model for the Instruction Mapping Tool

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

This paper describes the model designed for the instruction mapping tool, which can be used for generating the low level assembly code for the digital signal processing algorithms. The model is based on the Very Long Instruction Word architecture. The Texas Instrument TMS320C6678 was the pattern and finally was described with the created model. The paper is showing the parameters of the hardware resources and also the instruction set.

Klíčová slova

Processor model; Instruction mapping; VLIW

Autoři

MEGO, R.

Vydáno

10. 2. 2016

Nakladatel

University Carlos III of Madrid

Místo

Madrid

ISBN

978-84-608-6309-0

Kniha

Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)

Strany od

41

Strany do

44

Strany počet

4

URL

http://www.nesus.eu/proceedings

BibTex

@inproceedings{BUT123432,
  author="Roman {Mego}",
  title="Processor Model for the Instruction Mapping Tool",
  booktitle="Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)",
  year="2016",
  pages="41--44",
  publisher="University Carlos III of Madrid",
  address="Madrid",
  isbn="978-84-608-6309-0",
  url="http://www.nesus.eu/proceedings"
}