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STRNADEL, J.
Original Title
Nested Loops Degree Impact on RTL Digital Circuit Testability
Type
article in a collection out of WoS and Scopus
Language
English
Original Abstract
The existence of loops in a circuit structure causes problems in both test generation and application. Thus, the problem of identifying loops becomes an important task during testability analysis or, later, e.g., during allocation-for testability process. When nested loops occur in the circuit, it is necessary to accurately determine the most nested one to improve circuit testability significantly, with minimal design cost. This paper deals with the problem of identifying nested loops including their nesting degree in the register-transfer level (RTL) digital circuit structure as well as with the impact of such loops on the circuit testability.
Keywords
Testability, feedback loop, directed graph, ordered set, graph algorithm
Authors
RIV year
2003
Released
11. 2. 2003
Publisher
Elsevier Science
Location
Oxford
ISBN
0-08-044130-0
Book
Programmable Devices and Systems
Pages from
202
Pages to
207
Pages count
6
URL
https://www.fit.vut.cz/research/publication/7135/
BibTex
@inproceedings{BUT13789, author="Josef {Strnadel}", title="Nested Loops Degree Impact on RTL Digital Circuit Testability", booktitle="Programmable Devices and Systems", year="2003", pages="202--207", publisher="Elsevier Science", address="Oxford", isbn="0-08-044130-0", url="https://www.fit.vut.cz/research/publication/7135/" }