Přístupnostní navigace
E-přihláška
Vyhledávání Vyhledat Zavřít
Detail publikace
STRNADEL, J.
Originální název
Nested Loops Degree Impact on RTL Digital Circuit Testability
Typ
článek ve sborníku mimo WoS a Scopus
Jazyk
angličtina
Originální abstrakt
The existence of loops in a circuit structure causes problems in both test generation and application. Thus, the problem of identifying loops becomes an important task during testability analysis or, later, e.g., during allocation-for testability process. When nested loops occur in the circuit, it is necessary to accurately determine the most nested one to improve circuit testability significantly, with minimal design cost. This paper deals with the problem of identifying nested loops including their nesting degree in the register-transfer level (RTL) digital circuit structure as well as with the impact of such loops on the circuit testability.
Klíčová slova
Testability, feedback loop, directed graph, ordered set, graph algorithm
Autoři
Rok RIV
2003
Vydáno
11. 2. 2003
Nakladatel
Elsevier Science
Místo
Oxford
ISBN
0-08-044130-0
Kniha
Programmable Devices and Systems
Strany od
202
Strany do
207
Strany počet
6
URL
https://www.fit.vut.cz/research/publication/7135/
BibTex
@inproceedings{BUT13789, author="Josef {Strnadel}", title="Nested Loops Degree Impact on RTL Digital Circuit Testability", booktitle="Programmable Devices and Systems", year="2003", pages="202--207", publisher="Elsevier Science", address="Oxford", isbn="0-08-044130-0", url="https://www.fit.vut.cz/research/publication/7135/" }