Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs

conference paper

English

This paper presents and evaluates the possibility of automatic design of fault-tolerant systems from unhardened systems. We present an overview of our toolkit with its three main components: 1) fault-tolerant structures insertion (which we call helpers); 2) fault-tolerant structures selection (called guiders); and 3) automatic testbed generation, incorporating advanced acceleration techniques to accelerate the test and evaluation. Our approach is targeting complete independence on the HW description language and its abstraction level, however, for our case study, we focus on VHDL in combination with fine-grained n-modular redundancy. In the case study part of this paper, we proved that it is undoubtedly beneficial to select a proper fault tolerance method for each partition separately. Three experimental systems were developed with the usage of our method. Two of them achieved better reliability parameter while even lowering their chip area, compared to static allocation of equivalent fault tolerance technique type. In the case study, we target the best median time to failure, the so-called t50, however, our method is not dependent on this parameter and arbitrary optimization target can be selected, as soon as it is measurable.

Fault-Tolerant System Design, Electronic Design Automation, Redundancy Insertion, Redundancy Allocation, Multiple-choice Knapsack Problem, FPGA, VHDL, t50

LOJDA, J.; PÁNEK, R.; KOTÁSEK, Z.

1. 9. 2021

Institute of Electrical and Electronics Engineers

Palermo

978-1-6654-2703-6

Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021

549

552

4

https://www.fit.vut.cz/research/publication/12488/

DSD_2021_Lojda_et_al.pdf