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Publication detail
KRÁL, V.
Original Title
Saving area and power consumption in 65 nm digital standard cell library
Type
conference paper
Language
English
Original Abstract
This study aims to investigate multi-bit pulsed latches in comparison with multi-bit flip flops as one of the low-power solutions in 65 nm technology process. Topologies of pulse generators and multi-bit pulsed latches were investigated to find out which can be more suitable. The pulse generator was chosen because of its low power and a small area in comparison with other options. The pulse generator is made of a simple AND logical gate and a double-stacked inverter. The pulsed latch was also chosen because of its low power, small area, and reliability of the circuit. The chosen topology is modified PPCLA. Simulations of the chosen topology had shown that multi-bit flip flops could be replaced with more effective multi-bit pulsed latches.
Keywords
digital standard library, integrated circuits, chip development, low power methods, pulse generator, multi-bit pulsed latch
Authors
Released
26. 4. 2022
Publisher
Brno University of Technology, Faculty of Electrical Engineering and Communicatiopn
Location
Brno
ISBN
978-80-214-6029-4
Book
Proceedings I of the 28th Conference STUDENT EEICT 2022 General papers
Edition
1
Pages from
190
Pages to
193
Pages count
4
URL
https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2022_sbornik_1_v2.pdf
BibTex
@inproceedings{BUT188108, author="Vojtěch {Král}", title="Saving area and power consumption in 65 nm digital standard cell library", booktitle="Proceedings I of the 28th Conference STUDENT EEICT 2022 General papers", year="2022", series="1", pages="190--193", publisher="Brno University of Technology, Faculty of Electrical Engineering and Communicatiopn", address="Brno", isbn="978-80-214-6029-4", url="https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2022_sbornik_1_v2.pdf" }