Publication detail

BER Evaluation Embedded Module for Serial Links

KOLOUCH, J. KOLKA, Z. KUBÍČEK, M.

Original Title

BER Evaluation Embedded Module for Serial Links

Type

conference paper

Language

English

Original Abstract

The paper describes an embedded tester of Bit Error Rate (BER) in serial links based on the Spartan-3 FPGA device. The tester is suitable for long-term test without need of a human intervence. All management and measured data evaluation is done in a remote computer that is connected to the tester via Ethernet interface.

Keywords

bit error rate, BER test, serial link, LFSR, clock and data recovery

Authors

KOLOUCH, J.; KOLKA, Z.; KUBÍČEK, M.

RIV year

2006

Released

1. 9. 2006

Publisher

Institute of Circuit Theory, Metrology and Materials Science of the Technical University of Lodz, Poland

Location

Lodž

ISBN

83-921172-4-7

Book

International Conference on Signals and Electronic Systems, conference proceedings

Pages from

353

Pages to

355

Pages count

3

BibTex

@inproceedings{BUT20343,
  author="Jaromír {Kolouch} and Zdeněk {Kolka} and Michal {Kubíček}",
  title="BER Evaluation Embedded Module for Serial Links",
  booktitle="International Conference on Signals and Electronic Systems, conference proceedings",
  year="2006",
  pages="353--355",
  publisher="Institute of Circuit Theory, Metrology and Materials Science of the Technical University of Lodz, Poland",
  address="Lodž",
  isbn="83-921172-4-7"
}