Detail publikace

BER Evaluation Embedded Module for Serial Links

KOLOUCH, J. KOLKA, Z. KUBÍČEK, M.

Originální název

BER Evaluation Embedded Module for Serial Links

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper describes an embedded tester of Bit Error Rate (BER) in serial links based on the Spartan-3 FPGA device. The tester is suitable for long-term test without need of a human intervence. All management and measured data evaluation is done in a remote computer that is connected to the tester via Ethernet interface.

Klíčová slova

bit error rate, BER test, serial link, LFSR, clock and data recovery

Autoři

KOLOUCH, J.; KOLKA, Z.; KUBÍČEK, M.

Rok RIV

2006

Vydáno

1. 9. 2006

Nakladatel

Institute of Circuit Theory, Metrology and Materials Science of the Technical University of Lodz, Poland

Místo

Lodž

ISBN

83-921172-4-7

Kniha

International Conference on Signals and Electronic Systems, conference proceedings

Strany od

353

Strany do

355

Strany počet

3

BibTex

@inproceedings{BUT20343,
  author="Jaromír {Kolouch} and Zdeněk {Kolka} and Michal {Kubíček}",
  title="BER Evaluation Embedded Module for Serial Links",
  booktitle="International Conference on Signals and Electronic Systems, conference proceedings",
  year="2006",
  pages="353--355",
  publisher="Institute of Circuit Theory, Metrology and Materials Science of the Technical University of Lodz, Poland",
  address="Lodž",
  isbn="83-921172-4-7"
}