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Publication detail
HERRMAN, T.
Original Title
Formal Model of Testable Block
Type
conference paper
Language
English
Original Abstract
Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.
Keywords
RT level, Testable block, formal model, scan chain
Authors
RIV year
2006
Released
27. 4. 2006
Publisher
Faculty of Electrical Engineering and Communication BUT
Location
Brno
ISBN
80-214-3163-6
Book
Proceedings of 12th Conference Student EEICT 2006, Volume 4
Pages from
451
Pages to
455
Pages count
5
BibTex
@inproceedings{BUT22191, author="Tomáš {Herrman}", title="Formal Model of Testable Block", booktitle="Proceedings of 12th Conference Student EEICT 2006, Volume 4", year="2006", pages="451--455", publisher="Faculty of Electrical Engineering and Communication BUT", address="Brno", isbn="80-214-3163-6" }