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HERRMAN, T.
Originální název
Formal Model of Testable Block
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.
Klíčová slova
RT level, Testable block, formal model, scan chain
Autoři
Rok RIV
2006
Vydáno
27. 4. 2006
Nakladatel
Faculty of Electrical Engineering and Communication BUT
Místo
Brno
ISBN
80-214-3163-6
Kniha
Proceedings of 12th Conference Student EEICT 2006, Volume 4
Strany od
451
Strany do
455
Strany počet
5
BibTex
@inproceedings{BUT22191, author="Tomáš {Herrman}", title="Formal Model of Testable Block", booktitle="Proceedings of 12th Conference Student EEICT 2006, Volume 4", year="2006", pages="451--455", publisher="Faculty of Electrical Engineering and Communication BUT", address="Brno", isbn="80-214-3163-6" }