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Publication detail
HERRMAN, T.
Original Title
Testability Analysis Based on Formal Model
Type
conference paper
Language
English
Original Abstract
Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.
Keywords
formal model, RT level, testable block, testability analysis
Authors
RIV year
2006
Released
25. 9. 2006
Publisher
Faculty of Electrical Engineering and Informatics, University of Technology Košice
Location
Košice
ISBN
80-8073-598-0
Book
Proceedings of the Sevnth International Scientific Conference ECI 2006
Pages from
243
Pages to
248
Pages count
6
BibTex
@inproceedings{BUT22268, author="Tomáš {Herrman}", title="Testability Analysis Based on Formal Model", booktitle="Proceedings of the Sevnth International Scientific Conference ECI 2006", year="2006", pages="243--248", publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice", address="Košice", isbn="80-8073-598-0" }