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HERRMAN, T.
Originální název
Testability Analysis Based on Formal Model
Typ
článek ve sborníku ve WoS nebo Scopus
Jazyk
angličtina
Originální abstrakt
Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.
Klíčová slova
formal model, RT level, testable block, testability analysis
Autoři
Rok RIV
2006
Vydáno
25. 9. 2006
Nakladatel
Faculty of Electrical Engineering and Informatics, University of Technology Košice
Místo
Košice
ISBN
80-8073-598-0
Kniha
Proceedings of the Sevnth International Scientific Conference ECI 2006
Strany od
243
Strany do
248
Strany počet
6
BibTex
@inproceedings{BUT22268, author="Tomáš {Herrman}", title="Testability Analysis Based on Formal Model", booktitle="Proceedings of the Sevnth International Scientific Conference ECI 2006", year="2006", pages="243--248", publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice", address="Košice", isbn="80-8073-598-0" }