Publication detail

RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool

ŠKARVADA, J. HERRMAN, T. KOTÁSEK, Z.

Original Title

RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The paper presents testability analysis method which is based on partitioning circuit under analysis (CUA) to testable blocks (TBs). A formal approach utilizing the concepts of discrete mathematics is used for this purpose. The partitioning CUA into TBs is further exploited for power consumption optimization during test application. Software tools which were developed during the research and integrated into the third party design tool are also described. Experimental results gained from applying the methodology on selected benchmarks and practical designs are demonstrated.

Keywords

Testable block, power consumption estimation, test vectors generation, power consumption optimization.

Authors

ŠKARVADA, J.; HERRMAN, T.; KOTÁSEK, Z.

RIV year

2007

Released

12. 10. 2007

Publisher

Institute of Computing Technology, Chinese Academy of Sciences

Location

Beijing

Pages from

175

Pages to

181

Pages count

7

URL

https://www.fit.vut.cz/research/publication/8487/

BibTex

@inproceedings{BUT26071,
  author="Jaroslav {Škarvada} and Tomáš {Herrman} and Zdeněk {Kotásek}",
  title="RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool",
  booktitle="IEEE 8th Workshop on RTL and High Level Testing",
  year="2007",
  pages="175--181",
  publisher="Institute of Computing Technology, Chinese Academy of Sciences",
  address="Beijing",
  url="https://www.fit.vut.cz/research/publication/8487/"
}

Documents

wrtlt07.pdf